Patent US4237472A successfully refreshed from Google Patents.
US4237472A
Expired / Lapsed
US
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High performance electrically alterable read only memory (EAROM)
Assignee: RCA Corp
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Filing: 1979-03-12
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Granted: 1980-12-02
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Expires: 1999-03-12
Abstract
Abstract The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the emitter of a bipolar transistor to provide both bipolar collector-to-emitter breakdown voltage capability and bipolar radiation hardness while retaining MNOS memory performance.
Inventors
- 👤 Richard J. Hollingsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:19
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/409; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10W; H10W20/00; H10W20/20
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
330 words
An integrated circuit memory comprising: (A) a plurality of integrated circuit memory cells formed in a body of semiconductor material in an x-y array, each of which comprises: (i) a metal-nitride-oxide-semiconductor (MNOS) transistor comprising: (a) a semiconductor layer of a first conductivity type having a pair of spaced regions of opposite conductivity type formed therein, said spaced regions extending to a surface of said semiconductor layer; (b) a first insulating layer on the surface of said semiconductor layer, said first insulating layer extending at least between said pair of spaced regions; (c) a second insulating layer on the surface of said first insulating layer; and (d) a conductive gate on the surface of said second insulating layer; and (ii) a bipolar transistor comprising: (a) an emitter region of said opposite conductivity type, said emitter region comprising one of said spaced regions; (b) means for contacting said semiconductor layer, which semiconductor layer comprises the base of said bipolar transistor; (c) a collector region of said opposite conductivity type, said collector region extending into said semiconductor layer from a surface thereof, said collector region not lying between said pair of spaced regions and said collector region being separated from the one of said pair of spaced regions nearest to said collector region by a distance equal to the base width of said bipolar transistor; and (d) means for contacting said collector region; and (B) means for addressing an individual one of said plurality of cells, said means for addressing comprising a first series of conductive metal lines extending over the surface of the substrate in one direction and a second series of conductive metal lines extending over the surface of said substrate in a direction orthogonal to said one direction, said second series of conductive metal lines not extending over or under said first series of conductive metal lines, said second series of conductive metal lines being connected to conductive diffused regions which extend under said first series of conductive metal lines.
Claim 2
Dependent Claim
330 words
An integrated circuit memory comprising: (A) a plurality of integrated circuit memory cells formed in a body of semiconductor material in an x-y array, each of which comprises: (i) a metal-nitride-oxide-semiconductor (MNOS) transistor comprising: (a) a semiconductor layer of a first conductivity type having a pair of spaced regions of opposite conductivity type formed therein, said spaced regions extending to a surface of said semiconductor layer; (b) a first insulating layer on the surface of said semiconductor layer, said first insulating layer extending at least between said pair of spaced regions; (c) a second insulating layer on the surface of said first insulating layer; and (d) a conductive gate on the surface of said second insulating layer; and (ii) a bipolar transistor comprising: (a) an emitter region of said opposite conductivity type, said emitter region comprising one of said spaced regions; (b) means for contacting said semiconductor layer, which semiconductor layer comprises the base of said bipolar transistor; (c) a collector region of said opposite conductivity type, said collector region extending into said semiconductor layer from a surface thereof, said collector region not lying between said pair of spaced regions and said collector region being separated from the one of said pair of spaced regions nearest to said collector region by a distance equal to the base width of said bipolar transistor; and (d) means for contacting said collector region; and (B) means for addressing an individual one of said plurality of cells, said means for addressing comprising a first series of conductive metal lines extending over the surface of the substrate in one direction and a second series of conductive metal lines extending over the surface of said substrate in a direction orthogonal to said one direction, said second series of conductive metal lines not extending over or under said first series of conductive metal lines, said second series of conductive metal lines being connected to conductive diffused regions which extend under said first series of conductive metal lines.
Claim 3
Dependent Claim
27 words
The integrated circuit memory of claim 1 wherein said semiconductor layer is an N- type epitaxial layer formed on a substrate of a P type semiconductor material.
Claim 4
Dependent Claim
25 words
The integrated circuit memory of claim 1 wherein said semiconductor layer is an N- type well formed in a substrate of P type semiconductor material.
Claim 5
Dependent Claim
17 words
The integrated circuit memory of claim 3 wherein said first insulating layer is comprised of silicon dioxide.
Claim 6
Dependent Claim
22 words
The integrated circuit memory of claim 4 wherein said first insulating layer has a thickness of from 20 A to 60 A.
Claim 7
Dependent Claim
17 words
The integrated circuit memory of claim 5 wherein said second insulating layer is comprised of silicon nitride.
Claim 8
Dependent Claim
19 words
The integrated circuit memory of claim 6 wherein said second insulating layer has a thickness of about 450 A.
Claim 9
Dependent Claim
30 words
The integrated circuit memory of claim 7 wherein said means for contacting said emitter, said means for contacting said substrate and said conductive gate are all comprised of metal lines.
Claim 10
Dependent Claim
12 words
The integrated circuit memory of claim 8 wherein said metal is aluminum.
References Cited (Backward Citations)
US3622812A
Cited
US3877058A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-02 | 1984-06-02 | 1984-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-02 | 1988-06-02 | 1988-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-02 | 1992-06-02 | 1992-12-02 | $7700.00 | Window Closed / Lapsed |