Patent US4236294A successfully refreshed from Google Patents.
US4236294A
Expired / Lapsed
US
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High performance bipolar device and method for making same
Assignee: International Business Machines Corp
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Filing: 1979-03-16
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Granted: 1980-12-02
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Expires: 1999-03-16
Abstract
Abstract A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.
Inventors
- 👤 Narasipur G. Anantha
- 👤 Harsaran S. Bhatia
- 👤 James L. Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:59
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10P; H10P76/00; H10P76/40; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/131
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
153 words
A method for fabricating a high performance semiconductor device with small emitter-base spacing comprising: providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions; forming a base region in certain of said regions which contain a subcollector region; providing a mask over said body covering those regions designated to be the emitter and collector reach-through regions; forming a doped polysilicon layer through said mask wherein the said polysilicon layer makes ohmic contact to said base region; forming openings in said polysilicon layer over said designated regions; forming a layer of insulating material over said polysilicon layer; removing said mask where said emitter and collector reach-through are to be formed; forming said emitter in said base region and collector reach-through to said subcollector; and forming electrical contacts to said emitter and collector reach-through regions, and said polycrystalline silicon layer being the electrical contact to said base region.
Claim 2
Independent Claim
153 words
A method for fabricating a high performance semiconductor device with small emitter-base spacing comprising: providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions; forming a base region in certain of said regions which contain a subcollector region; providing a mask over said body covering those regions designated to be the emitter and collector reach-through regions; forming a doped polysilicon layer through said mask wherein the said polysilicon layer makes ohmic contact to said base region; forming openings in said polysilicon layer over said designated regions; forming a layer of insulating material over said polysilicon layer; removing said mask where said emitter and collector reach-through are to be formed; forming said emitter in said base region and collector reach-through to said subcollector; and forming electrical contacts to said emitter and collector reach-through regions, and said polycrystalline silicon layer being the electrical contact to said base region.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the said isolation is a dielectric material.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the said mask is formed of first and second layers of different dielectric material.
Claim 5
Dependent Claim
20 words
The method of claim 3 wherein the said first layer is silicon dioxide and the second layer is silicon nitride.
Claim 6
Independent Claim
211 words
A method for fabricating a high performance semiconductor device with small emitter-base spacing comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions; forming a base region in certain of said regions which contain a subcollector region; providing a mask of a first and second layer of different dielectric material over said body covering those regions designated to be the emitter and collector regions and open to those regions designated as base regions; forming a doped polysilicon layer over the surface of said body wherein the said polysilicon layer makes ohmic contact to said base region; removing said polysilicon layer located over said mask only where the emitter and collector reach-through contacts are to be made; forming a layer of material identical to the first layer over said polysilicon layer; removing said second dielectric layer of material from where said emitter and collector reach-through are to be formed; removing said first dielectric layer from where said emitter and collector reach-through are to be formed; forming said emitter in said base region and collector reach-through to said subcollector; and forming electrical contact to said emitter and collector reach-through regions, and said polycrystalline silicon layer being the electrical contact to said base region.
Claim 7
Independent Claim
211 words
A method for fabricating a high performance semiconductor device with small emitter-base spacing comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions; forming a base region in certain of said regions which contain a subcollector region; providing a mask of a first and second layer of different dielectric material over said body covering those regions designated to be the emitter and collector regions and open to those regions designated as base regions; forming a doped polysilicon layer over the surface of said body wherein the said polysilicon layer makes ohmic contact to said base region; removing said polysilicon layer located over said mask only where the emitter and collector reach-through contacts are to be made; forming a layer of material identical to the first layer over said polysilicon layer; removing said second dielectric layer of material from where said emitter and collector reach-through are to be formed; removing said first dielectric layer from where said emitter and collector reach-through are to be formed; forming said emitter in said base region and collector reach-through to said subcollector; and forming electrical contact to said emitter and collector reach-through regions, and said polycrystalline silicon layer being the electrical contact to said base region.
Claim 8
Dependent Claim
37 words
The method of claim 5 wherein said regions of monocrystalline silicon having said base region have the said base region dielectrically isolated from said collector reach-through therein and the said base region abuts said dielectric isolating regions.
Claim 9
Dependent Claim
15 words
The method of claim 5 wherein said polysilicon base electrical contact surrounds said emitter contact.
Claim 10
Dependent Claim
32 words
The method of claim 5 wherein said doped polysilicon layer is between about 1000 to 10,000 Angstroms in thickness and is doped with boron between about 10 19 to 10 21 atoms/cc.
Claim 11
Dependent Claim
13 words
The method of claim 8 wherein said transistor formed is an NPN type.
Claim 12
Dependent Claim
18 words
The method of claim 5 wherein said first layer is silicon dioxide and said second is silicon nitride.
Claim 13
Dependent Claim
31 words
The method of claim 8 wherein the emitter width and length dimensions are less than about two by two microns and the said emitter-base spacing is less than about 0.5 microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-02 | 1984-06-02 | 1984-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-02 | 1988-06-02 | 1988-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-02 | 1992-06-02 | 1992-12-02 | $7700.00 | Window Closed / Lapsed |