Method of and apparatus for testing electronic circuit assemblies and the like

Claim 3

A method as claimed in claim 1 and in which said driving is produced by a plurality of driving sources connected to a number of said nodes; and said sensing and detecting is also effected at a number of said nodes.

Claim 4

A method as claimed in claim 2 and in which said sequences are of duration of the order of 1-1000 milliseconds.

Claim 5

A method as claimed in claim 3 and in which said duration is of the order of 1 to 10 milliseconds with a ratio of duration to time between test responses of the order of 10 to 1-100 to 1.

Claim 6

Apparatus for the detection and location of faults of electronic assemblies comprised of electronic components interconnected by nodes by testing subsets of the components, said apparatus having, in combination: (a) driver circuit means connected to a number of said nodes for causing each node to assume voltages corresponding to true and false logic states of said components and a third state wherein the node voltage is that which would exist if there were no connection between said driver circuit means and node; (b) sensor circuit means connected to a number of said nodes for detecting the condition of a node corresponding to said true and false logic states and said third state; (c) control means for causing said driver circuit means to produce at each of a predetermined number of said connected nodes, a predetermined and uninterrupted sequence of signals corresponding to sequences of states of the true, false and third state; (d) means for comparing a sequence of detected states from said sensor circuit means to a sequence of predetermined states of the true, false and third state type; (e) and means for indicating the results of such comparisons.

Claim 7

Apparatus for the detection and location of faults of electronic assemblies comprised of electronic components interconnected by nodes by testing subsets of the components, said apparatus having, in combination: (a) driver circuit means connected to a number of said nodes for causing each node to assume voltages corresponding to true and false logic states of said components and a third state wherein the node voltage is that which would exist if there were no connection between said driver circuit means and node; (b) sensor circuit means connected to a number of said nodes for detecting the condition of a node corresponding to said true and false logic states and said third state; (c) control means for causing said driver circuit means to produce at each of a predetermined number of said connected nodes, a predetermined and uninterrupted sequence of signals corresponding to sequences of states of the true, false and third state; (d) means for comparing a sequence of detected states from said sensor circuit means to a sequence of predetermined states of the true, false and third state type; (e) and means for indicating the results of such comparisons.

Claim 8

Apparatus as claimed in claim 5 and in which the driver circuit means comprises a plurality of driver circuits connected to a number of said nodes and said sensor circuit means comprises a plurality of sensor circuits connected to a number of said nodes for detecting said states.

Claim 9

Apparatus as claimed in claim 6 and in which means is provided for inhibiting said comparing means or indicating means for a predetermined number of elements of said sensor circuit detected state sequences.

Claim 10

Apparatus as claimed in claim 5 wherein said control means includes synchronization and timing means for the temporal alignment of, and introduction of predetermined delays between, the elements of said sequences of driver circuit means signals and said sequences of comparing means comparisons.

Claim 11

Apparatus as claimed in claim 8 wherein said synchronization and timing means operate to synchronize said signals and comparisons with signals existing on said nodes of the said electronic assemblies.

Claim 12

Apparatus as claimed in claim 5 and in which said control means contains data storage means within which is stored the predetermined data required to specify said driver circuit means signal sequences and said comparing means comparing sequences, the arrangement of said data in said storage means being such as to associate with the particular nodes to which data applies and to the temporal order in which the sequence elements are to occur.

Claim 13

Apparatus as claimed in claim 6 and in which said control means contains data storage means within which is stored predetermined data required to specify the elements of said driver circuit means signal sequences and the said driver circuits to which they apply, as well as the elements of said comparing means comparing sequence and the sensor circuits to which they apply, the arrangement of said data in said data storage means being such as to associate with the temporal order in which said sequences are to occur.

Claim 14

Apparatus as claimed in claim 6 and in which said control means is connected to each of said plurality of sensor circuits, and said control means contains a plurality of data storage means each associated with one of said driver circuits and one of said sensor circuits, with the data storage means associated with said driver circuits containing data required to specify the elements of said driver circuit means signal sequence and stored in an arrangement so as to associate with the temporal order of said sequence.

Claim 15

Apparatus as claimed in claim 12 and in which said data storage means associated with each of said driver circuits and sensor circuits also contain data associated with the time of occurence of said sequence elements.

Claim 16

Apparatus as claimed in claim 5, wherein the control means includes means for causing said driver circuit means to produce sequences of duration of the order of 1-1000 milliseconds.

Claim 17

Apparatus as claimed in claim 14 and in which said duration is of the order of 1 to 100 milliseconds with a ratio of duration to time between test sequences of the order of 10 to 1-100 to 1.