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US4236224A
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Low roundoff noise digital filter
Assignee: Boeing North American Inc
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Filing: 1978-12-26
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Granted: 1980-11-25
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Expires: 1998-12-26
Abstract
Abstract An error feedback circuit is employed in a digital filter to significantly lower noise in the output by feeding back the least significant (roundoff) output bits of the quantizer rather than throwing these bits away as is done in the prior art. The feedback circuit for accomplishing this end result includes a digital delay circuit which receives the roundoff bits and delays these bits for a sampling sequence (Z -1 ) (as is also done for the rounded bits), a multiplier which multiplies the output of the delay circuit by a predetermined integer and an adder which subtracts the output of the multiplier from the delayed filtered digital output signal which has been multiplied by a predetermined constant.
Inventors
- 👤 Tien-Lin Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:19
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/04; H03H17/0461
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
193 words
In a digital filter for filtering a digital input signal, said digital filter having delay means for delaying an output signal thereof for the period of a predetermined signal sampling sequence, means for multiplying the output of said delaying means by a predetermined factor, quantizer means for quantizing a function of the output of said multiplying means, the output of said quantizer means including predetermined "rounded" bits and predetermined least significant "roundoff" bits, an improvement being means for feeding back a signal representing the "roundoff" bits for subtraction from a signal representing the "rounded" bits comprising: a delay device for delaying the "roundoff" bit output of said quantizer for a period equal to the period of said predetermined sequence, means for multiplying the output of said last mentioned delay device by a predetermined integer, and means interposed at the input of said quantizer for subtracting the output of said last mentioned multiplying means from the output of said first mentioned multiplying means, whereby the output of said subtracting means, which represents the difference between the rounded and roundoff bits for a previous sequence, is fed to the quantizer as the input signal thereto.
Claim 2
Dependent Claim
193 words
In a digital filter for filtering a digital input signal, said digital filter having delay means for delaying an output signal thereof for the period of a predetermined signal sampling sequence, means for multiplying the output of said delaying means by a predetermined factor, quantizer means for quantizing a function of the output of said multiplying means, the output of said quantizer means including predetermined "rounded" bits and predetermined least significant "roundoff" bits, an improvement being means for feeding back a signal representing the "roundoff" bits for subtraction from a signal representing the "rounded" bits comprising: a delay device for delaying the "roundoff" bit output of said quantizer for a period equal to the period of said predetermined sequence, means for multiplying the output of said last mentioned delay device by a predetermined integer, and means interposed at the input of said quantizer for subtracting the output of said last mentioned multiplying means from the output of said first mentioned multiplying means, whereby the output of said subtracting means, which represents the difference between the rounded and roundoff bits for a previous sequence, is fed to the quantizer as the input signal thereto.
Claim 3
Dependent Claim
140 words
The filter of claim 1 wherein said filter is a second order filter and includes second delay means for delaying the output of the first mentioned delay means for an additional period equal to a second sampling sequence and means for multiplying the output of the second delay means by a second predetermined factor, the first and second delayed and multiplied signals being summed together, and wherein the improvement further includes: a second delay device for delaying the output of the first mentioned delay device for a period equal to a second sampling sequence of operation, and means for multiplying the output of the second device by a second predetermined integer, and means for algebraically combining all said delayed and multiplied signals together, the output of said last mentioned summing means being fed to the quantizer as the input thereto.
Claim 4
Dependent Claim
135 words
In a digital filter for filtering a digital input signal, said filter having a quantizer with a predetermined least significant (roundoff) bit output and signficant (rounded) bit output wherein the rounded bit output is delayed, and multiplied by a predetermined factor, the improvement wherein the roundoff bits are delayed and fed back to provide a portion of the input to the quantizer comprising: a delay device for delaying the roundoff bit output of the quantizer for a period equal to a sampling sequence of the digital input signal, multiplier means for multiplying the output of said delay device by a predetermined integer, and means for subtracting the output of said multiplier means from the delayed and multiplied rounded bit output, the output of the subtracting means being fed to the quantizer as the input thereto.
Claim 5
Dependent Claim
135 words
In a digital filter for filtering a digital input signal, said filter having a quantizer with a predetermined least significant (roundoff) bit output and signficant (rounded) bit output wherein the rounded bit output is delayed, and multiplied by a predetermined factor, the improvement wherein the roundoff bits are delayed and fed back to provide a portion of the input to the quantizer comprising: a delay device for delaying the roundoff bit output of the quantizer for a period equal to a sampling sequence of the digital input signal, multiplier means for multiplying the output of said delay device by a predetermined integer, and means for subtracting the output of said multiplier means from the delayed and multiplied rounded bit output, the output of the subtracting means being fed to the quantizer as the input thereto.
Claim 6
Dependent Claim
36 words
The digital filter of claim 3 wherein the delayed rounded bit output is multiplied by a factor "a" and the delayed roundoff bit output is multiplied by an integer "k" wherein |a-k| is less than |a|.
Claim 7
Independent Claim
110 words
A method for lowering the noise in the output of a digital filter having a quantizer, the method comprising the steps of: delaying a digital output of the filter by a period equal to a digital sampling sequence, multiplying the delayed digital output by a predetermined factor (a), delaying the roundoff (least significant) bits in the output of the quantizer by a period equal to a digital sampling sequence of said digital filter, multiplying the delayed roundoff bits by a predetermined integer (k), subtracting said delayed and multiplied roundoff bits from the delayed and multiplied digital output, and feeding the difference of said subtraction as the input to the quantizer.
Claim 8
Independent Claim
110 words
A method for lowering the noise in the output of a digital filter having a quantizer, the method comprising the steps of: delaying a digital output of the filter by a period equal to a digital sampling sequence, multiplying the delayed digital output by a predetermined factor (a), delaying the roundoff (least significant) bits in the output of the quantizer by a period equal to a digital sampling sequence of said digital filter, multiplying the delayed roundoff bits by a predetermined integer (k), subtracting said delayed and multiplied roundoff bits from the delayed and multiplied digital output, and feeding the difference of said subtraction as the input to the quantizer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-25 | 1984-05-26 | 1984-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-25 | 1988-05-26 | 1988-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-25 | 1992-05-26 | 1992-11-25 | $7700.00 | Window Closed / Lapsed |