Patent US4232439A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4232439A Expired / Lapsed US ⏱️ 0.0 years remaining

Masking technique usable in manufacturing semiconductor devices

Assignee: VLSI Technology Research Association
•
Filing: 1977-11-29
•
Granted: 1980-11-11
•
Expires: 1997-11-29
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor layer different in material from a semiconductor substrate formed on at least one part of the surface of the substrate is partially removed in accordance with a planar configuration forming technique employing irradiation of a radiation such as light, electron beam or X-rays to form a residual layer and ion beams are applied to the upper surface or the substrate at an incidence angle less than 90 degrees so that a non-etching region is formed at the region of the substrate other than the region around and beneath said residual layer according to mutual relationships between the configuration of the residual layer and the incidence angle of the ion beams.

Inventors

  • 👤 Hiroshi Shibata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 23:09
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; C; C30; C30B; C30B31/00; C30B31/20; C30B31/22; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D10/00; H10D10/01; H10D10/051; H10D30/00; H10D30/01; H10D30/021; H10D30/022; H10D30/0221; H10D30/0223; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; Y; Y10; Y10S; Y10S148/00; Y10S148/143

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 225 words
A method of manufacturing a planar type semiconductor device having a monocrystalline semiconductor substrate of one conductivity type and having at least one intermediate region different in properties from side regions on both sides thereof, comprising the steps of: (a) forming a base, said base forming step including at least the forming of an oxide layer on one surface of said substrate; (b) forming a resist layer on said base, said resist layer having a thickness t; (c) selectively removing said resist layer to form a desired pattern including at least a pair of pattern portions spaced apart by a distance L substantially corresponding to the width of said intermediate region to form a window; (d) introducing impurities of the other conductivity into said side regions of said substrate by irradiating said substrate with impurity ion beams obliquely at an angle equal to or less than tan -1 (t/L) with respect to said substrate surface; (e) removing said oxide layer on said side regions by irradiating said substrate with etching ion beams at the same angle as in step (d) to form contact holes on said side regions; (f) depositing ohmic electrode material over said substrate surface; (g) removing said resist pattern portions; and (h) said method further comprising the step of irradiating said substrate with vertical impurity ion beams of the other conductivity type.
Claim 2
Independent Claim 225 words
A method of manufacturing a planar type semiconductor device having a monocrystalline semiconductor substrate of one conductivity type and having at least one intermediate region different in properties from side regions on both sides thereof, comprising the steps of: (a) forming a base, said base forming step including at least the forming of an oxide layer on one surface of said substrate; (b) forming a resist layer on said base, said resist layer having a thickness t; (c) selectively removing said resist layer to form a desired pattern including at least a pair of pattern portions spaced apart by a distance L substantially corresponding to the width of said intermediate region to form a window; (d) introducing impurities of the other conductivity into said side regions of said substrate by irradiating said substrate with impurity ion beams obliquely at an angle equal to or less than tan -1 (t/L) with respect to said substrate surface; (e) removing said oxide layer on said side regions by irradiating said substrate with etching ion beams at the same angle as in step (d) to form contact holes on said side regions; (f) depositing ohmic electrode material over said substrate surface; (g) removing said resist pattern portions; and (h) said method further comprising the step of irradiating said substrate with vertical impurity ion beams of the other conductivity type.
Claim 3
Dependent Claim 57 words
The method as defined in claim 1 wherein said base forming step consists of the forming of an oxide layer on one surface of said substrate, wherein the first-mentioned impurity introducing step results in the formation of source and drain regions and wherein said irradiation with vertical impurity ion beams is performed after said resist removing step.
Claim 4
Dependent Claim 87 words
The method as defined in claim 1, wherein said base forming step comprises the forming of an oxide layer on one surface of said substrate followed by the forming of a conductive layer on said oxide layer, wherein the first-mentioned impurity introducing step results in the formation of source and drain regions, wherein the conductive layer underlying said resist pattern portions is removed in said resist removing step, and wherein the irradiation of said substrate with vertical impurity ion beams is performed after said resist removing step.
Claim 5
Dependent Claim 74 words
The method as defined in claim 1, wherein said base forming step comprises the forming of an oxide layer on said substrate followed by said step of irradiating said substrate with vertical impurity ion beams of said other conductivity type, said method further comprising the step, immediately prior to said oxide removing step, of implanting ions of said one conductivity type into said window area by irradiating said window area with vertical ion beams.

References Cited (Backward Citations)

US3258898A Cited
US3914857A Cited
US4086694A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-11-11 1984-05-12 1984-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-11-11 1988-05-12 1988-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-11-11 1992-05-12 1992-11-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag