Patent US4231102A successfully refreshed from Google Patents.
US4231102A
Expired / Lapsed
US
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Cordic FFT processor
Assignee: Raytheon Co
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Filing: 1978-12-21
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Granted: 1980-10-28
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Expires: 1998-12-21
Abstract
Abstract An apparatus for performing a Fourier transform using Cordic techniques. Digital words are pipelined through serial add/subtract stages to provide vector rotations without trignometric lookup tables or multiply operations. The throughput of an FFT butterfly calculation is increased over prior art digital processors. A plurality of apparatus may be pipelined in a system to further increase the throughput rate. Also, the apparatus may be programmed to perform vector rotations through a plurality of angles thus providing the capability to compute FFT's of varying numbers of points.
Inventors
- 👤 Paul C. Barr
- 👤 Herbert L. Groginsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:44
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
163 words
In combination: a plurality of pairs of arithmetic elements adapted for input of two digital words, each of said elements providing as an output either a sum or difference of two input digital words; a storage means connected to the output of each of said elements; means for connecting said pairs of elements and storage means in a series, said connecting means hardwire connecting bits of the contents of storage means to inputs of both of the elements of the next sequential pair of elements in said series; and said connecting means comprising means for bit transpositioning where necessary such that if the contents of two said storage means of a pair of elements are X i and Y i where i is the number of the arithmetic element pair in said series, the outputs of the next sequential pair of arithmetic elements in said series will be X i ±2 i Y i and Y i ±2 -i X 1 , respectively.
Claim 2
Dependent Claim
163 words
In combination: a plurality of pairs of arithmetic elements adapted for input of two digital words, each of said elements providing as an output either a sum or difference of two input digital words; a storage means connected to the output of each of said elements; means for connecting said pairs of elements and storage means in a series, said connecting means hardwire connecting bits of the contents of storage means to inputs of both of the elements of the next sequential pair of elements in said series; and said connecting means comprising means for bit transpositioning where necessary such that if the contents of two said storage means of a pair of elements are X i and Y i where i is the number of the arithmetic element pair in said series, the outputs of the next sequential pair of arithmetic elements in said series will be X i ±2 i Y i and Y i ±2 -i X 1 , respectively.
Claim 3
Dependent Claim
18 words
The combination in accordance with claim 1 further comprising clocking means for clocking digital words through said series.
Claim 4
Dependent Claim
26 words
The combination in accordance with claim 2 wherein the arithmetic operation of each of said arithmetic elements is determined by a logic control to each element.
Claim 5
Dependent Claim
26 words
The combination in accordance with claim 3 wherein said logic control for each element is opposite the logic control for the other element of said pair.
Claim 6
Dependent Claim
14 words
The combination in accordance with claim 4 wherein said storage means is a register.
Claim 7
Dependent Claim
43 words
The combination in accordance with claim 5 further comprising means for controlling said logic control to each of said elements such that the contents in the last said registers in said series satisfy the CORDIC equations for vector rotation through a given angle.
Claim 8
Independent Claim
166 words
A system for performing a Fourier transform comprising: a plurality of computational stages, each stage comprising means for performing arithmetic add and subtract operations on a pair of input digital words and means for storing the results of said operations; means for coupling said storing means of one stage to the next sequential stage of said series, said coupling means comprising means for hardwire connecting bits of the contents of said storing means of said one stage to inputs of both of said elements in said next sequential stage, said connecting means comprising means for bit transpositioning as required such that if the contents in said storing means of one stage are respectively X i and Y i where i is the number of the stage in the series, the coupled inputs to the next sequential stage are X i , Y i , 2 -i X i and 2 -i Y i ; and means for clocking pairs of digital word inputs through said stages.
Claim 9
Independent Claim
166 words
A system for performing a Fourier transform comprising: a plurality of computational stages, each stage comprising means for performing arithmetic add and subtract operations on a pair of input digital words and means for storing the results of said operations; means for coupling said storing means of one stage to the next sequential stage of said series, said coupling means comprising means for hardwire connecting bits of the contents of said storing means of said one stage to inputs of both of said elements in said next sequential stage, said connecting means comprising means for bit transpositioning as required such that if the contents in said storing means of one stage are respectively X i and Y i where i is the number of the stage in the series, the coupled inputs to the next sequential stage are X i , Y i , 2 -i X i and 2 -i Y i ; and means for clocking pairs of digital word inputs through said stages.
Claim 10
Dependent Claim
28 words
The system of claim 7 wherein said means for performing arithmetic add and subtract operations comprises means for providing an add or subtract operation determined by logic control.
Claim 11
Dependent Claim
17 words
The system recited in claim 8 further comprising a control memory, said memory providing said logic control.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |