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US4075630A Expired / Lapsed US ⏱️ 0.0 years remaining

Signal processor

Assignee: Raytheon Co
•
Filing: 1976-09-01
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Granted: 1978-02-21
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Expires: 1996-09-01
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Abstract

Abstract A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signals are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.

Inventors

  • 👤 Gerald N. Shapiro
  • 👤 Bertram J. Goldstone
  • 👤 Joseph D. Simone
  • 👤 Edward E. Spignese

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 19:09
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S13/52; G01S13/522; G01S13/524; G01S13/53; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/292

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 215 words
In a radar-guided missile having a radar receiver for receiving radar return signals, a signal processor for processing such radar return signals to provide a discrete Fast Fourier Transform on such radar return signals, such signal processor comprising: (a) means for separating such radar return signals into two quadrature components; (b) means for converting each sample of such components into a corresponding digital word; (c) means for converting each digital word into a sequence of binary digits; (d) clock means for producing a sequence of binary control signals; (e) scaling means, responsive to a portion of the sequence of binary control signals, for scaling each digital word by a factor selected in accordance with the binary control signals to form a sequence of binary digits corresponding to such scaled digital word; (f) memory means for storing and serially retrieving such latter sequence of binary digits; (g) data decoder means, responsive to at least a portion of the sequence of binary control signals, the serially retrieved sequence of binary digits and a second sequence of binary digits corresponding to a different one of the digital words, for producing a sequence of binary digits corresponding to an arithmetic operation of the digital words in the two sequences of binary digits responded to by the data decoder means.
Claim 2
Dependent Claim 215 words
In a radar-guided missile having a radar receiver for receiving radar return signals, a signal processor for processing such radar return signals to provide a discrete Fast Fourier Transform on such radar return signals, such signal processor comprising: (a) means for separating such radar return signals into two quadrature components; (b) means for converting each sample of such components into a corresponding digital word; (c) means for converting each digital word into a sequence of binary digits; (d) clock means for producing a sequence of binary control signals; (e) scaling means, responsive to a portion of the sequence of binary control signals, for scaling each digital word by a factor selected in accordance with the binary control signals to form a sequence of binary digits corresponding to such scaled digital word; (f) memory means for storing and serially retrieving such latter sequence of binary digits; (g) data decoder means, responsive to at least a portion of the sequence of binary control signals, the serially retrieved sequence of binary digits and a second sequence of binary digits corresponding to a different one of the digital words, for producing a sequence of binary digits corresponding to an arithmetic operation of the digital words in the two sequences of binary digits responded to by the data decoder means.
Claim 3
Dependent Claim 15 words
The signal processor recited in claim 1 wherein the scale means includes a serial-parallel multiplier.

References Cited (Backward Citations)

US3987285A Cited
US3987442A Cited
US3950750A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-02-20 1981-08-22 1982-02-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-02-20 1985-08-22 1986-02-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-02-20 1989-08-22 1990-02-21 $7700.00 Window Closed / Lapsed

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