Interface unit facilitating communication between data processor and program-interrupting peripheral unit

Claim 1

An interface unit for facilitating communication in an electronic data-handling system between a processor having a program memory and one of a plurality of peripheral units adapted to transmit data to said processor, the latter being provided with preferential circuitry for assigning different priority ratings to certain of said peripheral units and being programmed to emit a succession of instructions respectively directed to said peripheral units for inviting the transmission of data available thereat, such data transmission requiring an interruption of the program of the processor, the latter having two output leads carrying a two-bit portion of an input/output instruction generated by said program memory, said interface unit comprising: a register for the storage of first, second, third and fourth bit combinations respectively representing a plurality of states including a preparatory state, an intermediate state, an active state and a quiescent state; a decoder connected to an output of said register for respectively converting said first, second, third and fourth bit combinations into a first switching signal denoting said preparatory state, a second switching signal denoting said intermediate state, a third switching signal denoting said active state and a fourth switching signal denoting said quiescent state; loading means with input connections to said decoder and to said output leads of the processor for entering said first bit combination in said register upon coincidence of said fourth switching signal with an instruction addressing the associated peripheral unit; first gating means with input connections to said decoder and to the associated peripheral unit for emitting an enabling signal to said register upon coincidence of said first switching signal with a data-ready signal from said associated peripheral unit; second gating means with input connections to said decoder and to said preferential circuitry for emitting an enabling signal to said register upon coincidence of said second switching signal with an authorization signal indicating the absence of overriding priorities; third gating means with input connections to said decoder and to the processor for emitting an enabling signal to said register upon coincidence of said third switching signal with a confirmation signal indicative of a program interruption, said third gating means also establishing a path for the transmission of the address of the associated peripheral unit to the processor preparatorily to the initiation of direct communication therebetween; a binary incrementer connected to the output of said register for converting said first, second and third bit combinations into said second, third and fourth bit combinations, respectively; and feedback means connecting said incrementer to said register for entering therein the converted bit combinations in response to the enabling signal from any of said gating means, said feedback means including a multiplexer with a first input connected to said incrementer and a second input connected to said output leads of the processor, said multiplexer being switchable by said loading means from said first input to said second input in the presence of said instruction and said fourth switching signal.