Patent US4069497A successfully refreshed from Google Patents.
Patent US4229699A successfully refreshed from Google Patents.
US4229699A
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Multiple clock selection system
Assignee: EMC Corp
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Filing: 1978-05-22
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Granted: 1980-10-21
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Expires: 1998-05-22
Abstract
Abstract A system for switching among a plurality of input clock signals to produce an output clock signal which avoids the presence of spurious signals during the process of switching from one to another of said plurality of input clock signals. When it is desired to switch from one input clock signal to a new input clock signal, clock output logic is inhibited from supplying any clock output signal for a selected time period, after which the newly selected input clock signal is supplied as the clock output signal. The time period is dependent on the clock pulse rate of the newly selected input clock signal and is sufficiently long to assure that no spurious signals will occur thereafter.
Inventors
- 👤 John M. Frissell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:31
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H; H03; H03K; H03K3/00; H03K3/64; H03K3/72; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
130 words
Clock signal selection circuitry comprising means for providing at least two input clock signals, each having a different clock rate; means for selecting one of said at least two input clock signals; means responsive to said selected input clock signal for supplying an output clock signal corresponding to said selected input clock signal; single delay means responsive to said selected input clock signal for inhibiting the supplying of said output clock signal for a selected time period after a different one of said at least two input clock signals has been selected by said selecting means; said output clock signal supplying means being responsive to a newly selected input clock signal for supplying, after said selected time period, an output clock signal corresponding to said newly selected input clock signal.
Claim 2
Dependent Claim
130 words
Clock signal selection circuitry comprising means for providing at least two input clock signals, each having a different clock rate; means for selecting one of said at least two input clock signals; means responsive to said selected input clock signal for supplying an output clock signal corresponding to said selected input clock signal; single delay means responsive to said selected input clock signal for inhibiting the supplying of said output clock signal for a selected time period after a different one of said at least two input clock signals has been selected by said selecting means; said output clock signal supplying means being responsive to a newly selected input clock signal for supplying, after said selected time period, an output clock signal corresponding to said newly selected input clock signal.
Claim 3
Dependent Claim
45 words
Clock signal selection circuitry in accordance with claim 1 wherein said single delay means includes counter means responsive to said newly selected input clock signal for providing a counter output signal which prevents the supplying of an output clock signal during said selected time period.
Claim 4
Dependent Claim
29 words
Clock signal selection circuitry in accordance with claims 1 or 2 wherein said selected time period is dependent upon the clock rate of the newly selected input clock signal.
Claim 5
Dependent Claim
31 words
Clock signal selection circuitry in accordance with claims 1 or 2 wherein said selected time period is equal to a selected number of cycles of said newly selected input clock signal.
Claim 6
Dependent Claim
17 words
Clock signal selection circuitry in accordance with claim 4 wherein said selected number of cycles is four.
Claim 7
Dependent Claim
23 words
Clock signal selection circuitry in accordance with claim 1 wherein said selected time period is a fixed multiple of the newly selected clock.
Claim 8
Dependent Claim
39 words
Clock signal selection circuitry in accordance with claims 1, 2, 5 or 6 wherein said input clock signal providing means provides two input clock signals, said output clock signal supplying means supplying one of said two input clock signals.
Claim 9
Dependent Claim
29 words
Clock signal selection circuitry in accordance with claim 3 wherein said selected time period is equal to a selected number of cycles of said newly selected input clock signal.
Claim 10
Dependent Claim
35 words
Clock signal selection circuitry in accordance with claim 3 wherein said input clock signal providing means provides two input clock signals, said output clock signal supplying means supplying one of said two input clock signals.
Claim 11
Dependent Claim
35 words
Clock signal selection circuitry in accordance with claim 4 wherein said input clock signal providing means provides two input clock signals, said output clock signal supplying means supplying one of said two input clock signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-21 | 1984-04-21 | 1984-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-21 | 1988-04-21 | 1988-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-21 | 1992-04-21 | 1992-10-21 | $7700.00 | Window Closed / Lapsed |