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US4228462A Expired / Lapsed US ⏱️ 0.0 years remaining

Line oscillator synchronizing circuit

Assignee: US Philips Corp
•
Filing: 1978-11-14
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Granted: 1980-10-14
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Expires: 1998-11-14
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Abstract

Abstract A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.

Inventors

  • 👤 Jan van Straaten

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 23:25
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 255 words
A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase discriminator.
Claim 2
Dependent Claim 255 words
A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase discriminator.
Claim 3
Dependent Claim 49 words
A television receiver as claimed in claim 1, wherein said controlling means comprises a differential amplifier for amplifying the difference between the second smoothed voltage and a reference voltage, the time position of an edge of the oscillator signal being controllable by the output signal of the differential amplifier.
Claim 4
Dependent Claim 32 words
A television receiver as claimed in claim 1, wherein the time constant of the second low-pass filter is at least ten times smaller than the time constant of the first low-pass filter.
Claim 5
Dependent Claim 96 words
A television receiver as claimed in claim 1, wherein the gate means comprises an AND-gate, a first input terminal of which is the second input terminal of the gate means and a second input terminal of said AND-gate is supplied with a signal originating from the controllable oscillator, and an OR-gate, a first input terminal of which is the first input terminal of the gate means and a second terminal of said OR-gate is connected to the output terminal of the AND-gate, the output terminal of the OR-gate being the output terminal of the gate means.
Claim 6
Dependent Claim 34 words
A television receiver as claimed in claim 1, wherein said line sychronizing circuit further comprises an amplifier for amplfying the first smoothed voltage, the output voltage of which is supplied to the pulse generator.
Claim 7
Dependent Claim 34 words
A television receiver as claimed in any of the preceeding claims, wherein said line synchronizing circuit, with the exception of capacitors forming a part of said low-pass filters, is integrated in a semiconductor body.

References Cited (Backward Citations)

US4024343A Cited
US3991270A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-10-14 1984-04-14 1984-10-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-10-14 1988-04-14 1988-10-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-10-14 1992-04-14 1992-10-14 $7700.00 Window Closed / Lapsed

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