Random access MOS memory cell using double level polysilicon

Claim 1

In an N-channel silicon-gate MOS memory cell of the type formed at a face of a silicon body and having one MOS transistor and capacitance means, the MOS transistor including a polycrystalline silicon gate and including a source-to-drain path formed in said face, a heavily doped N+ region as one end of the source-to-drain path in said face, the N+ region also forming an elongated sense line running generally parallel to said face, the capacitance means including a polycrystalline silicon plate which is separated from said face by a thin silicon oxide dielectric and including a capacitor region in said face beneath said plate, the plate being part of an elongated strip of polycrystalline silicon which forms part of the capacitance means of a number of like cells along said face, the elongated strip running generally parallel to the sense line, the strip being connected to a reference potential, and elongated conductive means connected to the gate and extending along the face, the improvement comprising: an anisotropically-etched V-groove in said face of the silicon body, the capacitor region being defined in the surface of the V-groove, and the source-to-drain path of the MOS transistor being defined in a side wall of the V-groove, the gate being spaced from the capacitor region, first and second levels of polycrystalline silicon included in the cell, with the second level at least partially overlying the first level but insulated therefrom, the first level providing said plate and said elongated strip, the second level providing the gate of the MOS transistor, the other end of the source-to-drain path of the MOS transistor being provided by an edge of the capacitor region without a heavily-doped N+ region.