Patent US4225795A successfully refreshed from Google Patents.
US4225795A
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Coincidence circuit for a protective relay circuit
Assignee: General Electric Co
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Filing: 1978-05-30
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Granted: 1980-09-30
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Expires: 1998-05-30
Abstract
Abstract The coincidence circuit includes negative and positive signal processing means. The negative and positive signal processing means each includes level detector circuit means for developing separate level detector output signals for each one of a plurality of a-c input signals when each one of the plurality of a-c input signals is of a negative or positive value respectively greater than predetermined negative or positive threshold levels. The predetermined threshold levels are of different magnitude for at least some of the a-c input signals. AND circuit means is coupled to receive the level detector output signals of the negative and positive signal processing means for developing AND circuit output signals respectively representative of negative and positive phase coincidence of the a-c input signals with threshold level attainment. OR circuit means is coupled to receive the AND circuit output signals for developing an OR output signal continuously representative of the phase coincidence of the a-c input signals. The coincidence circuit operates directly from a-c input signals of relatively low signal strength. In a preferred embodiment, a plurality of comparators are employed to receive four a-c input signals for use in a ground distance protective relaying application. In this embodiment, the predetermined threshold levels are in the millivolt range. Other embodiments are disclosed.
Inventors
- 👤 Marvin F. Keeney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:18
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H02; H02H; H02H3/00; H02H3/38; H02H3/382; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
401 words
In a protective relay circuit of the type employing a timer circuit and, a coincidence circuit for receiving a plurality of a.c. input signals and developing a coincidence output signal representative of the phase coincidence of the plurality of a.c. input signals, which coincidence circuit comprises: (a) negative signal processing means including: (i) first level detector circuit means for developing a separate first level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality a.c. input signals is of a negative value greater than a predetermined negative threshold value, said predetermined negative threshold value being of a different value for at least some of said a.c. input signals, (ii) first AND circuit means for receiving said first level detector output signals and developing a first AND output signal representative of negative phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a negative value greater than said predetermined negative threshold values, (b) positive signal processing means including: (i) second level detector circuit means for developing a separate second level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality of a.c. input signals is of a positive value greater than a predetermined positive threshold value, said predetermined positive threshold value being of a different value for at least some of said a.c. input signals, (ii) second AND circuit means for receiving said second level detector output signals and developing a second AND output signal representative of positive phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a positive value greater than said predetermined positive threshold values, and (c) OR circuit means coupled to receive said first and second AND output signals for developing an OR circuit output signal in response to said first or second AND output signal, said OR circuit output signal being representative of the phase coincidence of said plurality of a.c. input signals wherein said predetermined negative and positive threshold values are exceeded for the respective negative and positive portions of said a.c. input signals, said OR circuit output signal being coupled to a timer circuit which measures the duration of said OR circuit output signal and develops an output signal when the phase coincidence occurs for a predetermined minimum time.
Claim 2
Dependent Claim
401 words
In a protective relay circuit of the type employing a timer circuit and, a coincidence circuit for receiving a plurality of a.c. input signals and developing a coincidence output signal representative of the phase coincidence of the plurality of a.c. input signals, which coincidence circuit comprises: (a) negative signal processing means including: (i) first level detector circuit means for developing a separate first level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality a.c. input signals is of a negative value greater than a predetermined negative threshold value, said predetermined negative threshold value being of a different value for at least some of said a.c. input signals, (ii) first AND circuit means for receiving said first level detector output signals and developing a first AND output signal representative of negative phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a negative value greater than said predetermined negative threshold values, (b) positive signal processing means including: (i) second level detector circuit means for developing a separate second level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality of a.c. input signals is of a positive value greater than a predetermined positive threshold value, said predetermined positive threshold value being of a different value for at least some of said a.c. input signals, (ii) second AND circuit means for receiving said second level detector output signals and developing a second AND output signal representative of positive phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a positive value greater than said predetermined positive threshold values, and (c) OR circuit means coupled to receive said first and second AND output signals for developing an OR circuit output signal in response to said first or second AND output signal, said OR circuit output signal being representative of the phase coincidence of said plurality of a.c. input signals wherein said predetermined negative and positive threshold values are exceeded for the respective negative and positive portions of said a.c. input signals, said OR circuit output signal being coupled to a timer circuit which measures the duration of said OR circuit output signal and develops an output signal when the phase coincidence occurs for a predetermined minimum time.
Claim 3
Dependent Claim
25 words
A coincidence circuit in accordance with claim 1 in which at least some of said predetermined threshold values are less than about 7 volts dc.
Claim 4
Dependent Claim
25 words
A coincidence circuit in accordance with claim 2 in which at least some of said predetermined threshold values are less than about 0.1 volt dc.
Claim 5
Dependent Claim
33 words
A coincidence circuit in accordance with claim 1 for receiving three a-c input signals in which said OR circuit output signal is representative of the phase coincidence of said three a-c input signals.
Claim 6
Dependent Claim
33 words
A coincidence circuit in accordance with claim 1 for receiving four a-c input signals in which said OR circuit output signal is representative of the phase coincidence of said four a-c input signals.
Claim 7
Dependent Claim
35 words
A coincidence circuit in accordance with claim 1 in which at least some of said first and second level detector output signals are coupled to said first and second AND circuit means through switching means.
Claim 8
Dependent Claim
72 words
A coincidence circuit in accordance with claim 6 in which said switching means includes means for coupling at least one of said level detector output signals indicating threshold attainment of one polarity to said AND circuit means which develops said AND output signal representative of phase coincidence of the opposite polarity such that said OR circuit output signal is representative of opposite phase coincidence of at least some of said input signals.
Claim 9
Dependent Claim
204 words
A coincidence circuit in accordance with claim 1 in which, said negative signal processing means includes a plurality of first comparators, one of said comparators being provided for each one of said a-c input signals, each of said comparators including a non-inverting input, an inverting input, and an output, the non-inverting inputs being coupled through separate first resistors to ground potential, the non-inverting inputs being coupled to a source of negative potential through separate second resistors, the inverting inputs being coupled through separate third resistors to receive said plurality of a-c input signals, said positive signal processing means includes a plurality of second comparators, one of said comparators being provided for each one of said a-c input signals, each of said comparators including a non-inverting input, an inverting input, and an output, the inverting inputs being coupled through separate fourth resistors to ground potential, the inverting inputs being coupled to a source of positive potential through separate fifth resistors, the non-inverting inputs being coupled through separate sixth resistors to receive said plurality of a-c input signals, and at least some of said outputs of said first comparators being coupled together and at least some of said outputs of said second comparators being coupled together.
Claim 10
Dependent Claim
141 words
A coincidence circuit in accordance with claim 8 in which said first AND circuit means comprises a first NPN transistor having its base coupled to receive at least some of said outputs of said first comparators, said base being coupled through a seventh resistor to a source of positive potential, the emitter of said first transistor being coupled to a source of negative potential, said second AND circuit means comprises a second NPN transistor having its base coupled to receive at least some of said outputs of said second comparators, said base being coupled through an eighth resistor to said source of positive potential, the emitter of said second transistor being coupled to said source of negative potential, and said collectors of said first and second transistors being coupled together and through a ninth resistor to said source of positive potential.
Claim 11
Dependent Claim
97 words
A coincidence circuit in accordance with claim 9 in which said OR circuit comprises a third NPN transistor having its base coupled to said collectors of said first and second NPN transistors, the emitter of said third NPN transistor being coupled through a tenth resistor to said source of negative potential, the collector of said third NPN transistor being coupled to said source of positive potential through an eleventh resistor and coupled to ground potential through a clamping diode, wherein the signal appearing at the collector of said third NPN transistor comprises said OR circuit output signal.
Claim 12
Dependent Claim
63 words
A coincidence circuit in accordance with claim 8 in which said predetermined negative threshold values are adjustably determined by the values of said first and second resistors and the magnitude of said negative source of potential and said predetermined positive threshold values are adjustably determined by the values of said fourth and fifth resistors and the magnitude of said positive source of potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-30 | 1984-03-31 | 1984-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-30 | 1988-03-31 | 1988-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-30 | 1992-03-31 | 1992-09-30 | $7700.00 | Window Closed / Lapsed |