Phase sequence detector for three-phase AC power system

Claim 2

A phase sequence detector for monitoring the phase sequence of the three phase currents supplied by a three-phase AC power supply to a phase-sensitive three-phase load to determine if a predetermined desired phase sequence exists, thereby determining whether the power supply is correctly connected to the load, comprising: a flip-flop having set and reset operating states and having first, second and third inputs for actuating said flip-flop to its two operating states, said flip-flop triggering to its set operating state in response to the application of an actuating signal to said second input at the same time that a certain signal condition is present on said first input and triggering to its reset state in response to the application of an actuating signal to said second input when a given signal condition is present on said third input; means responsive to the three phase currents supplied to the three-phase load for providing first, second and third phase-displaced, control signals each of which is a function of and represents a respective one of the three phase currents; means for applying said first, second and third control signals to said first, second and third inputs, respectively, said first and second control signals effecting actuation of said flip-flop to its set operating state when said predetermined desired phase sequence is present and said second and third control signals causing actuation of said flip-flop to its reset state if any other phase sequence exists; and means responsive to and controlled by said flip-flop for providing an indication of the operating state of said flip-flop.

Claim 3

A digital logic phase sequence detector for monitoring the phase sequence of the three phase currents supplied by a three-phase AC power supply to a phase-sensitive, three-phase load to determine if a predetermined desired phase sequence exists, thereby determining whether the power supply is correctly connected to the load, comprising: a flip-flop having set and reset operating states and having first, second and third inputs for actuating said flip-flop to its two operating states, said flip-flop triggering to its set operating state if a positive-going pulse transition is applied to said second input when said first input is established at a logic 1 signal level and actuating to its reset state if a positive-going pulse transition is applied to said second input when said third input is established at a logic 1 signal level, means responsive to the three phase currents supplied to the three-phase load for producing first, second and third phase-displaced, generally rectangular shaped logic signals each of which alternates between logic 1 and logic 0 levels and each of which represents and is a function of a respective one of the three phase currents, the logic 1 pulse components of said first logic signal embracing the positive-going transitions of said second logic signal and the logic 1 pulse components of said second logic signal overlapping the positive-going transitions of said third logic signal when said predetermined desired phase sequence is present; means for applying said first, second and third logic signals to said first, second and third inputs, respectively, to establish said flip-flop in its set operating state if said predetermined desired phase sequence exists and in its reset operating state if said predetermined desired phase sequence is absent; and means controlled by said flip-flop for providing an indication of the operating state of said flip-flop.

Claim 4

A digital logic phase sequence detector for monitoring the phase sequence of the three phase currents supplied by a three-phase AC power supply to a phase-sensitive, three-phase load to determine if a predetermined desired phase sequence exists, thereby determining whether the power supply is correctly connected to the load, comprising: a flip-flop having set and reset operating states and having first, second and third inputs for actuating said flip-flop to its two operating states, said flip-flop triggering to its set operating state if a positive-going pulse transition is applied to said second input when said first input is established at a logic 1 signal level and actuating to its reset state if a positive-going pulse transition is applied to said second input when said third input is established at a logic 1 signal level, means responsive to the three phase currents supplied to the three-phase load for producing first, second and third phase-displaced, generally rectangular shaped logic signals each of which alternates between logic 1 and logic 0 levels and each of which represents and is a function of a respective one of the three phase currents, the logic 1 pulse components of said first logic signal embracing the positive-going transitions of said second logic signal and the logic 1 pulse components of said second logic signal overlapping the positive-going transitions of said third logic signal when said predetermined desired phase sequence is present; means for applying said first, second and third logic signals to said first, second and third inputs, respectively, to establish said flip-flop in its set operating state if said predetermined desired phase sequence exists and in its reset operating state if said predetermined desired phase sequence is absent; and means controlled by said flip-flop for providing an indication of the operating state of said flip-flop.

Claim 5

A digital logic phase sequence detector according to claim 2 and including means controlled by said flip-flop for disconnecting the load from the AC power supply when said flip-flop is in its reset operating state.

Claim 6

A digital logic phase sequence detector according to claim 2 in which said flip-flop is a J-K flip-flop having J, C and K inputs respectively constituting said first, second and third inputs.

Claim 7

A digital logic phase sequence detector according to claim 2 in which said first, second and third logic signals are produced by three voltage comparators to which are applied, respectively, three sinusoidal signals each of which is developed from a respective one of the three phase currents.