US3633115A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital voltage controlled oscillator producing an output clock which follows the phase variation of an input clock
Assignee: TDK Micronas GmbH
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Filing: 1970-04-22
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Granted: 1972-01-04
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Expires: 1990-04-22
Abstract
Abstract The digital VCO provides an output clock following the phase variation of an input clock where both the input and output clocks have the same average repetition frequency but rapid phase input clock variations are smoothed in the output clock. A local clock is produced having a repetition frequency equal to a given multiple L of the nominal repetition frequency of the output clock. A binary counter divides this local clock by a value N and through logic circuitry coupled to the binary counter and to the local clock provides a first clock signal having a repetition frequency equal to L times the nominal repetition frequency of the output clock with a missing pulse every N pulses and, in addition thereto, a second clock signal containing only, the missing pulses. A binary counter chain driven in an appropriate manner as described below by these clock signals provides the phase adjusted output clock with steps of 1/L period. The phase varying input clock and the phase adjusted output clock are each divided by a given factor M and phase compared by a clocked RS flip-flop thus, providing an input output phase comparison modulo M cycles. The output of this flip-flop is coupled to a JK flipflop and is clocked by the missing pulse with the resultant output thereof being applied to a modulo-2 adder inserted between predetermined stages of the binary counterchain to bring about the desired phase adjustment of the output clock so as to follow the phase variation of the input clock. The binary counterchain is also driven by the first clock signal.
Inventors
- 👤 Marvin A Epstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
151 words
A digital voltage controlled oscillator to produce an output clock having a given repetition frequency following the phase variation of an input clock having said given repetition frequency comprising: a source of said input clock; first means to generate a local clock having a repetition frequency equal to a given multiple L of the nominal value of said given repetition frequency and to generate at least a first timing signal having a given activating interval, where L is an integer greater than one; second means coupled to said first means responsive to said local clock to produce said output clock; and third means coupled to said source, said first means and said second means responsive to said first timing signal and the phase relation between said input clock and said output clock to control said second means to cause said output clock to follow the phase variation of said input clock.
Claim 2
Dependent Claim
151 words
A digital voltage controlled oscillator to produce an output clock having a given repetition frequency following the phase variation of an input clock having said given repetition frequency comprising: a source of said input clock; first means to generate a local clock having a repetition frequency equal to a given multiple L of the nominal value of said given repetition frequency and to generate at least a first timing signal having a given activating interval, where L is an integer greater than one; second means coupled to said first means responsive to said local clock to produce said output clock; and third means coupled to said source, said first means and said second means responsive to said first timing signal and the phase relation between said input clock and said output clock to control said second means to cause said output clock to follow the phase variation of said input clock.
Claim 3
Dependent Claim
47 words
An oscillator according to claim 1, wherein said first means includes means to generate said local clock having a missing pulse every N pulses of said local clock, where N is an integer greater then one, and to generate as said first timing signal said missing pulse.
Claim 4
Dependent Claim
101 words
An oscillator according to claim 2, wherein said second means includes a binary counter chain; and said third means includes a digital phase comparator coupled to said source and the output of said counterchain to detect the phase relation between said input clock and said output clock, and a decision circuit coupled to said first means, said phase comparator and a given location in said counter chain responsive to the output of said phase comparator and said missing pulse to adjust the counting of said counter chain according to the detected phase relation between said input clock and said output clock.
Claim 5
Dependent Claim
52 words
An oscillator according to claim 2, wherein said first means includes a generator of said local clock, a binary counter coupled to said generator to divide the frequency of said clock by N, and logic circuitry coupled to said generator and said counter to generate said local clock and said missing pulse.
Claim 6
Dependent Claim
193 words
An oscillator according to claim 4, wherein said logic circuitry includes a first RS flip-flop having its set input coupled to said counter, a second RS flip-flop having its set input coupled to the ''''1'''' output of said first flip-flop and its clock input coupled to said generator, the ''''1'''' output of said second flip-flop being coupled to the reset input of said second flip-flop, a first AND having two inputs and an output coupled to the reset input of said first flip-flop, one of said two inputs being coupled to said generator and the other of said two inputs being coupled to the ''''1'''' output of said second flip-flop, a second AND having two inputs and an output to provide said missing pulse, one of said two inputs being coupled to the ''''1'''' output of said second flip-flop and the other of said two inputs being coupled to said generator, and a third AND having two inputs and an output to provide said local clock, one of said two inputs being coupled to the ''''0'''' output of said second flip-flop and the other of said two inputs being coupled to said generator.
Claim 7
Dependent Claim
15 words
An oscillator according to claim 2, wherein said second means includes a binary counter chain.
Claim 8
Dependent Claim
121 words
An oscillator according to claim 6, wherein said third means includes a digital phase comparator coupled to said source and the output of said counterchain to detect the phase relation between said input clock and said output clock, a JK flip-flop having a set input, a reset input and a clock input, said set and reset inputs being coupled to the output of said phase comparator and said clock input being coupled to said first means responsive to said missing pulse, and a modulo-2 adder coupled to the ''''1'''' and ''''0'''' outputs of said JK flip-flop and between predetermined stages of said counterchain to adjust the counting of said counterchain to provide said output clock at the output of said counterchain.
Claim 9
Dependent Claim
51 words
An oscillator according to claim 7, wherein said phase comparator includes an RS flip-flop having a set input, a reset input and a clock input at least one of said set and reset inputs being coupled to said source and said clock input being coupled to the output of said counterchain.
Claim 10
Dependent Claim
55 words
An oscillator according to claim 8, further including a first binary counter having a given count coupled between said source and both said set and reset inputs of said RS flip-flop, and a second binary counter having said given count coupled between the output of said counterchain and said clock input of said RS flip-flop.
Claim 11
Dependent Claim
141 words
An oscillator according to claim 9, wherein said first means further generates a second timing signal defining an interval during which said RS flip-flop cannot change its state, and further including a first AND having two inputs and an output coupled to the set input of said RS flip-flop, one of said two inputs being coupled to one of the two outputs of said first counter and the other of said two inputs being coupled to said first means responsive to said second timing signal, and a second AND having two inputs and an output coupled to the reset input of said RS flip-flop, one of said two inputs being coupled to the other of the two outputs of said first counter and the other of said two inputs being coupled to said first means responsive to said second timing signal.
Claim 12
Dependent Claim
114 words
An oscillator according to claim 2, wherein said third means includes a digital phase comparator coupled to said source and the output of said second means to detect the phase relation between said input clock and said output clock, a JK flip-flop having a set input, a reset input and a clock input, said set and reset inputs being coupled to the output of said phase comparator and said clock input being coupled to said first means responsive to said missing pulse, and a modulo-2 adder coupled to the ''''1'''' and ''''0'''' outputs of said JK flip-flops and to a given location within said second means to adjust the phase of said output clock.
Claim 13
Dependent Claim
416 words
An oscillator according to claim 2, wherein said first means includes a generator of said local clock, a first binary counter coupled to said generator to divide the frequency of said clock by N, a first RS flip-flop having its set input coupled to said first counter, a second RS flip-flop having its set input coupled to the ''''1'''' output of said first flip-flop, the ''''1'''' output of said second flip-flop being coupled to the reset input of said second flip-flop. a NOT coupled between said generator and the clock input of said second flip-flop, a first AND having two inputs and an output coupled to the reset input of said first flip-flop, one of said two inputs being coupled to said generator and the other of said two inputs being coupled to the ''''1'''' output of said second flip-flop, a second AND having two inputs and an output to provide said missing pulse, one of said two inputs being coupled to the ''''1'''' output of said second flip-flop and the other of said two inputs being coupled to said generator, and a third AND having two inputs and an output to provide said local clock, one of said two inputs being coupled to the ''''0'''' output of said second flip-flop and the other of said two inputs being coupled to said generator; said second means includes a binary counter chain having its input coupled to the output of said third AND; and said third means includes a second binary counter having a given count coupled to said source, a third binary counter having said given count coupled to the output of said counterchain, a third RS flip-flop having a set input, a reset input and a clock input, said set input being coupled to the ''''1'''' output of said second counter, said reset input being coupled to the ''''0'''' output of said second counter and said clock input being coupled to one of the ''''1'''' and ''''0'''' outputs of said third counter, a JK flip-flop having a set input, a reset input and a clock input, said set and reset inputs being coupled to the ''''1'''' output of said third RS flip-flop and said clock input being coupled to the output of said second AND, and a modulo-2 adder coupled to the ''''1'''' and ''''0'''' outputs oF said JK flip-flop and between predetermined stages of said counterchain to adjust the counting of said counterchain to provide said output clock at the output of said counterchain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |