Patent US4222117A successfully refreshed from Google Patents.
US4222117A
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US
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Data pulse receiver arrangement
Assignee: US Philips Corp
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Filing: 1978-09-22
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Granted: 1980-09-09
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Expires: 1998-09-22
Abstract
Abstract A data pulse receiver arrangement is disclosed having a ringing circuit for establishing a clock pulse signal for data pulses which occur in a serial bit stream in a received information signal. The receiver arrangement is characterized in that comparator means are included for comparing the voltage across the ringing circuit with a reference voltage and for actuating a switching means for decoupling the input signal from the ringing circuit to prevent over-excitation thereof.
Inventors
- 👤 Richard E. F. Bugg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:01
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
191 words
A data pulse receiver arrangement for the acquisition of data pulses which occur in a serial bit stream in a received information signal in which one level of the signal represents a binary value `1` and another level of the signal represents a binary value `0`, said arrangement including a data pulse clock generator in the form of a ringing circuit which comprises a tuned circuit arranged for oscillation at a predetermined clock pulse frequency and voltage-to-current convertor means responsive to voltage input pulses derived from received data pulses to produce current pulses for exciting the tuned circuit to maintain its oscillation, which data pulse receiver arrangement is characterized in that said ringing circuit further comprises comparator means for comparing the voltage produced across the tuned circuit with a reference voltage, and switching means responsive to an output received from the comparator means when the voltage across the tuned circuit exceeds the reference voltage to interrupt the current pulses to the tuned circuit until said output from the comparator has been terminated due to oscillation damping of the tuned circuit reducing the voltage across it to below the reference voltage again.
Claim 2
Dependent Claim
191 words
A data pulse receiver arrangement for the acquisition of data pulses which occur in a serial bit stream in a received information signal in which one level of the signal represents a binary value `1` and another level of the signal represents a binary value `0`, said arrangement including a data pulse clock generator in the form of a ringing circuit which comprises a tuned circuit arranged for oscillation at a predetermined clock pulse frequency and voltage-to-current convertor means responsive to voltage input pulses derived from received data pulses to produce current pulses for exciting the tuned circuit to maintain its oscillation, which data pulse receiver arrangement is characterized in that said ringing circuit further comprises comparator means for comparing the voltage produced across the tuned circuit with a reference voltage, and switching means responsive to an output received from the comparator means when the voltage across the tuned circuit exceeds the reference voltage to interrupt the current pulses to the tuned circuit until said output from the comparator has been terminated due to oscillation damping of the tuned circuit reducing the voltage across it to below the reference voltage again.
Claim 3
Dependent Claim
101 words
A data pulse receiver arrangement as claimed in claim 1, wherein said ringing circuit comprises first and second transistors which are connected as a long-tailed pair and form said comparator means, a third transistor which is connected in the common emitter connection of the first and second transistors and forms said voltage-to-current convertor means, and a fourth transistor which forms said switching means and is connected as an emitter-follower to apply the voltage produced across the tuned circuit to the base of either said first or second transistor of which said reference voltage is applied to the base of the other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-09 | 1984-03-10 | 1984-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-09 | 1988-03-10 | 1988-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-09 | 1992-03-10 | 1992-09-09 | $7700.00 | Window Closed / Lapsed |