← Back to Patent Explorer
US3573634A Expired / Lapsed US ⏱️ 0.0 years remaining

Timing of regenerator and receiver apparatus for an unrestricted digital communication signal

Assignee: AT&T Inc
•
Filing: 1968-09-04
•
Granted: 1971-04-06
•
Expires: 1988-09-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A dedicated burst of timing pulses is multiplexed in each frame of an unrestricted digital signal to supply timing information to receiver and regenerator circuits in a time division communication system. When the burst appears in the received signal the output of a tuned RLC circuit builds up to a threshold level. A threshold detector then triggers a time control circuit, which in one embodiment of the invention is a counter circuit and in another embodiment of the invention is a pair of monostable multivibrator circuits, to gate the digital signal to a timing recovery circuit for the duration of the burst.

Inventors

  • 👤 Todd L Rachel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 23:36
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/10; H04L7/08; H04L7/02; H04L7/027; H04L7/033; H04L7/041; H04L7/046

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 225 words
In combination: a source of an input digital signal having a plurality of timing pulses which occur in groups at predetermined intervals in said digital signal; a tuned circuit connected to receive said digital signal for producing an output signal which reaches a predetermined threshold level in response to the reception of a predetermined number of said timing pulses in each of said groups in said digital signal; a threshold circuit connected to receive the output signal from said tuned circuit for generating an output signal when the output of said tuned circuit reaches said predetermined threshold level; a timing recovery circuit for providing an output signal at a predetermined frequency with respect to said input digital signal including first gating means for controlling said timing recovery circuit so that the frequency of said output signal is adjusted only when said first gating means is activated; second gating means for controlling the transmission of said digital signal to said tuned circuit; means responsive to said threshold circuit for activating said first gating means in the presence of said groups of timing pulses so that the frequency of said output signal is determined by said timing pulses; and means responsive to said threshold circuit for providing an inhibit signal to said second gating means when said groups of timing pulses in said digital signal are absent.
Claim 2
Dependent Claim 225 words
In combination: a source of an input digital signal having a plurality of timing pulses which occur in groups at predetermined intervals in said digital signal; a tuned circuit connected to receive said digital signal for producing an output signal which reaches a predetermined threshold level in response to the reception of a predetermined number of said timing pulses in each of said groups in said digital signal; a threshold circuit connected to receive the output signal from said tuned circuit for generating an output signal when the output of said tuned circuit reaches said predetermined threshold level; a timing recovery circuit for providing an output signal at a predetermined frequency with respect to said input digital signal including first gating means for controlling said timing recovery circuit so that the frequency of said output signal is adjusted only when said first gating means is activated; second gating means for controlling the transmission of said digital signal to said tuned circuit; means responsive to said threshold circuit for activating said first gating means in the presence of said groups of timing pulses so that the frequency of said output signal is determined by said timing pulses; and means responsive to said threshold circuit for providing an inhibit signal to said second gating means when said groups of timing pulses in said digital signal are absent.
Claim 3
Dependent Claim 261 words
In combination: a source of an input digital signal divided into time frames having a predetermined burst of timing pulses multiplexed in each frame, each of said bursts having first and second groups of pulses; a tuned circuit connected to receive said digital signal; discharge means responsive to said first group of pulses in each of said bursts for discharging said tuned circuit to a predetermined reference potential, said tuned circuit rising from said reference potential to a predetermined threshold level in response to a predetermined plurality of timing pulses in said second group of pulses in each of said bursts; a threshold circuit for generating an output signal when the output of said tuned circuit reaches said predetermined threshold level; a timing recovery circuit for providing an output signal at a predetermined frequency with respect to said input digital signal including first gating means for controlling said timing recovery circuit so that said frequency of said output signal is adjusted only when said first gating means is activated; second gating means for controlling the transmission of said digital signal to said tuned RLC circuit; means responsive to said threshold circuit for activating said first gating means in the presence of said second group of pulses in each of said bursts so that the frequency of said output signal of said timing recovery circuit is determined by said group of pulses; and means responsive to said threshold circuit for providing an inhibit signal to said second gating means when said second group of pulses in each of said bursts is absent
Claim 4
Dependent Claim 261 words
In combination: a source of an input digital signal divided into time frames having a predetermined burst of timing pulses multiplexed in each frame, each of said bursts having first and second groups of pulses; a tuned circuit connected to receive said digital signal; discharge means responsive to said first group of pulses in each of said bursts for discharging said tuned circuit to a predetermined reference potential, said tuned circuit rising from said reference potential to a predetermined threshold level in response to a predetermined plurality of timing pulses in said second group of pulses in each of said bursts; a threshold circuit for generating an output signal when the output of said tuned circuit reaches said predetermined threshold level; a timing recovery circuit for providing an output signal at a predetermined frequency with respect to said input digital signal including first gating means for controlling said timing recovery circuit so that said frequency of said output signal is adjusted only when said first gating means is activated; second gating means for controlling the transmission of said digital signal to said tuned RLC circuit; means responsive to said threshold circuit for activating said first gating means in the presence of said second group of pulses in each of said bursts so that the frequency of said output signal of said timing recovery circuit is determined by said group of pulses; and means responsive to said threshold circuit for providing an inhibit signal to said second gating means when said second group of pulses in each of said bursts is absent
Claim 5
Dependent Claim 72 words
Apparatus in accordance with claim 2 wherein said means for providing said inhibit signal to said second gating means and said means for activating said first gating means in a counter circuit which provides said inhibit signal for said second gating means in a first frame and which anticipates the burst occurring in a second succeeding frame in said digital signal to activate said first gating means in said timing recovery circuit.
Claim 6
Dependent Claim 58 words
Apparatus in accordance with claim 2 wherein said discharge means includes a delay element, a logic gate and a discharge gate, said delay element and said logic gate combining to detect said first group of pulses in said burst and said discharge gate being responsive to said delay element and said logic gate to discharge said tuned circuit.
Claim 7
Dependent Claim 304 words
Apparatus for detecting a dedicated burst of timing pulses in a multilevel digital signal and for gating a portion of said burst to a timing recovery circuit having a variable frequency output signal comprising in combination: a first gating means included in said timing recovery circuit for controlling said variable frequency output signal so that said variable frequency is adjusted only when said first gating means is activated; a tuned circuit connected to receive said digital signal; a second gating means for controlling the transmission of said digital signal to said tuned circuit; discharge means connected to said tuned circuit and responsive to a first group of pulses in said dedicated burst for discharging said tuned circuit to a predetermined reference potential, said tuned circuit rising from said reference potential to a predetermined threshold level in response to a predetermined number of timing pulses in a second portion of said dedicated burst; a threshold circuit connected to said tuned circuit for providing an output signal when the output of said tuned circuit reaches said predetermined threshold level; a delay element for providing a time delay in the transmission path of said digital signal to said timing recovery circuit, said delay being equal to the time said tuned circuit takes to reach said predetermined threshold level from said reference potential; a first monostable multivibrator circuit responsive to said signal from said threshold circuit foR directly activating said first gating means in the presence of said second group of pulses in said burst so that the frequency of said signal from said timing recovery circuit is controlled by said pulses; and a second monostable multivibrator circuit responsive to said signal from said tuned circuit for inhibiting said second gating means for a predetermined interval when said second group of pulses in said timing burst is absent.
Claim 8
Dependent Claim 304 words
Apparatus for detecting a dedicated burst of timing pulses in a multilevel digital signal and for gating a portion of said burst to a timing recovery circuit having a variable frequency output signal comprising in combination: a first gating means included in said timing recovery circuit for controlling said variable frequency output signal so that said variable frequency is adjusted only when said first gating means is activated; a tuned circuit connected to receive said digital signal; a second gating means for controlling the transmission of said digital signal to said tuned circuit; discharge means connected to said tuned circuit and responsive to a first group of pulses in said dedicated burst for discharging said tuned circuit to a predetermined reference potential, said tuned circuit rising from said reference potential to a predetermined threshold level in response to a predetermined number of timing pulses in a second portion of said dedicated burst; a threshold circuit connected to said tuned circuit for providing an output signal when the output of said tuned circuit reaches said predetermined threshold level; a delay element for providing a time delay in the transmission path of said digital signal to said timing recovery circuit, said delay being equal to the time said tuned circuit takes to reach said predetermined threshold level from said reference potential; a first monostable multivibrator circuit responsive to said signal from said threshold circuit foR directly activating said first gating means in the presence of said second group of pulses in said burst so that the frequency of said signal from said timing recovery circuit is controlled by said pulses; and a second monostable multivibrator circuit responsive to said signal from said tuned circuit for inhibiting said second gating means for a predetermined interval when said second group of pulses in said timing burst is absent.

References Cited (Backward Citations)

US2992341A Cited
US3189835A Cited
US3136861A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-04-05 1974-10-05 1975-04-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-04-05 1978-10-05 1979-04-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-04-05 1982-10-05 1983-04-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag