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US4220968A
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Circuit for generating a constant reference oscillation from a video signal affected by a time error
Assignee: Deutsche Thomson OHG
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Filing: 1978-09-27
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Granted: 1980-09-02
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Expires: 1998-09-27
Abstract
Abstract A circuit for generating a constant reference oscillation from a video signal affected by a time error, comprising, a cut-off stage for receiving the video signal affected by the time error and outputting sync pulses and vertical sync pulses, a first frequency divider connected to the cutoff stage for receiving the vertical sync pulses and outputting divided frequency pulses and a first comparator stage connected to the first frequency divider for receiving the divided frequency pulses. The first comparator stage has an output connected to an oscillator and the oscillator, in turn, has an output connected to a second frequency divider which is also connected to an input of the first comparator stage. A second comparator stage is connected between the cutoff stage sync pulses and an output of the oscillator for producing an output and a clock oscillator is connected to the output and, in turn, is connected to a bucket chain which receives the video signal affected by the time error and outputs a video signal which is free of the time error.
Inventors
- 👤 Werner Scholz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:19
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/95; H04N5/953
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
183 words
A circuit for generating a constant reference oscillation from a video signal affected by a time error, comprising, a cutoff stage for receiving a video signal affected by a time error and outputting sync pulses and vertical sync pulses, a first frequency divider connected to said cutoff stage for receiving said vertical sync pulses and outputting divided frequency pulses, a first comparator stage connected to said first frequency divider for receiving said divided frequency pulses and having an output, an oscillator connected to said output of said comparator stage and itself having an output, a second frequency divider connected to said output of said oscillator and having an output connected to said first comparator stage, a second comparator stage connected between said output of said oscillator and said sync pulses of said cutoff stage and itself having an output, a clock oscillator connected to said output of said second comparator stage, and a bucket chain connected to an output of said clock oscillator and receiving the video signal affected by the time error for outputting a video signal free of the time error.
Claim 2
Dependent Claim
183 words
A circuit for generating a constant reference oscillation from a video signal affected by a time error, comprising, a cutoff stage for receiving a video signal affected by a time error and outputting sync pulses and vertical sync pulses, a first frequency divider connected to said cutoff stage for receiving said vertical sync pulses and outputting divided frequency pulses, a first comparator stage connected to said first frequency divider for receiving said divided frequency pulses and having an output, an oscillator connected to said output of said comparator stage and itself having an output, a second frequency divider connected to said output of said oscillator and having an output connected to said first comparator stage, a second comparator stage connected between said output of said oscillator and said sync pulses of said cutoff stage and itself having an output, a clock oscillator connected to said output of said second comparator stage, and a bucket chain connected to an output of said clock oscillator and receiving the video signal affected by the time error for outputting a video signal free of the time error.
Claim 3
Dependent Claim
92 words
A circuit for generating a substantially constant reference oscillation from a time error affected video signal, specifically for time error compensation with a recording unit, having an oscillator which is synchronized by video signal cutoff sync pulses via a phase-locked loop control circuit with phase comparator for conducting a phase comparison between the video signal cutoff sync pulses and the output of the oscillator, where the time error has a periodic sequence, comprising, means connected to said oscillator for periodicially phase-controlling it by the time error period or an integral multiple thereof.
Claim 4
Dependent Claim
92 words
A circuit for generating a substantially constant reference oscillation from a time error affected video signal, specifically for time error compensation with a recording unit, having an oscillator which is synchronized by video signal cutoff sync pulses via a phase-locked loop control circuit with phase comparator for conducting a phase comparison between the video signal cutoff sync pulses and the output of the oscillator, where the time error has a periodic sequence, comprising, means connected to said oscillator for periodicially phase-controlling it by the time error period or an integral multiple thereof.
Claim 5
Dependent Claim
52 words
A circuit, as claimed in claim 2, wherein said oscillator oscillates with line frequency f H or a fraction 1/m·f H of said frequency, and the phase comparison for phase control is effective at vertical frequency f v or a fraction 1/2n·f v of said frequency where n and m are integers.
Claim 6
Dependent Claim
43 words
A circuit, as claimed in claim 2, wherein said phase-control is effective at line frequency f H or 1/m·f H , and including a periodically opened gate which is set in the path of the phase control loop, where m is an integer.
Claim 7
Dependent Claim
18 words
A circuit, as claimed in claim 2, wherein said phase-control is gated applicably only during vertical blanking time.
Claim 8
Dependent Claim
28 words
A circuit, as claimed in claim 1, wherein for the phase-comparison in the phase-locked loop, sawtooth voltages at frequency 1/m·f H are used, where m is an integer.
Claim 9
Dependent Claim
30 words
A circuit, as claimed in claim 2, wherein the phase comparison is gated at a frequency 1/2n·f v , and wherein the vertical frequency f r and n are integers.
Claim 10
Dependent Claim
32 words
A circuit, as claimed in claim 2, wherein on using the circuit with a video recording unit, a switchover to periodic control is effectively delayed after switching in the video recording unit.
Claim 11
Dependent Claim
31 words
A circuit, as claimed in claim 2, wherein the time error varies between positive and negative values and said phase-control is gated only when the time error passes its zero value.
Claim 12
Dependent Claim
45 words
A circuit, as claimed in claim 2, wherein said gating period is so timed that at least one full period of frequency 1/m·f H coincides with the gating time, where m is an integer, where f H is the line of frequency of the oscillator.
Claim 13
Dependent Claim
43 words
A circuit, as claimed in claim 2, wherein the circuit can operate both under constant and gated phase control by means of a switchable on- and off gate, and the gated control is switched in only at a steady state and interference-free operation.
Claim 14
Dependent Claim
56 words
A circuit, as claimed in claim 11, wherein the transition from steady control to gated control and vice versa is controlled by a frequency standard stage which monitors whether the oscillator originating pulses 1/m·H 2 and the video signal (BAS 1 )-derived pulses 1/m·H 1 appear in exactly alternating sequence, and where m is an integer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-02 | 1984-03-03 | 1984-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-02 | 1988-03-03 | 1988-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-02 | 1992-03-03 | 1992-09-02 | $7700.00 | Window Closed / Lapsed |