Television signal clocked delay line for delay by an integer number of horizontal scanning lines driven by a pilot signal

Claim 1

In a circuit for delaying, by an integral number of line scanning periods, a recorded video signal being played back from a video recorder whose output speed is subjected to fluctuation in the duration of a line scanning period, and including a memory composed of a plurality of memory elements and arranged to store the signal representing one video picture line at a time, with each memory element storing a respective segment of such picture line signal, means for connecting the input of said memory to the output of said recorder, and clock pulse generator means connected to the memory for producing a train of clock pulses during each line scanning period, each pulse causing the signal segment stored in a respective element during a preceding line scanning period to be read out, the improvement comprising circuit means connected between said recorder and said clock pulse generator means for receiving a component of said video signal for detecting the actual, presently existing line period duration of said signal and for controlling the frequency of said clock pulse generator means such that the number of pulses in the train of clock pulses per line scanning period of the video signal is substantially constant and the clock pulses have a repetition rate directly proportional to the duration of the actual, presently existing line scanning period, and for thereby causing the delay produced by said memory to always correspond to said existing line scanning period of the video signal applied to said memory and derived from said recorder whereby any fluctuation in the speed of said video recorder and in the line scanning period may be instantly compensated for.