Narrow channel MOS devices and method of manufacturing

Claim 2

A field effect transistor comprising: a body of semiconductor material having a nonplanar surface that includes adjacent areas of relatively higher and lower elevation joined by a slope, a first region of one conductivity type in said body underlying said higher elevation area, a second region of the same conductivity type in said body underlying said lower elevation area, one of said first and second regions serving as a source region and the other as a drain for said transistor, and an implanted layer of the opposite conductivity type disposed intermediate said first and second regions, said layer having an upturned margin terminating at said slope and serving as a channel region for said transistor.

Claim 3

The transistor of claim 1, further comprising: an insulating layer covering at least the portion of said slope that includes the termination of said implanted layer, and a gate electrode disposed on said insulating layer.

Claim 4

The transistor of claim 1, wherein said channel and drain regions are spaced apart to provide a drift region between them.

Claim 5

An integrated circuit structure comprising: a semiconductor sustrate having a laterally extending upper surface, said surface including a first, higher elevation portion and a second, lower elevation portion joined to the first by a slope, a first region of one conductivity type extending into said substrate at said first surface portion, a second region of the same conductivity type extending into said substrate at said second surface portion, one of said first and second regions serving as a source region and the other as a drain region of a field effect device in said structure, a thin implanted layer of the opposite conductivity type disposed intermediate said first and second regions, said layer having an upwardly-extending portion that terminates at said slope and serves as a channel region for said device, and a gate electrode disposed overlying at least the portion of said slope that includes the termination of said layer.

Claim 6

An integrated circuit structure comprising: a semiconductor sustrate having a laterally extending upper surface, said surface including a first, higher elevation portion and a second, lower elevation portion joined to the first by a slope, a first region of one conductivity type extending into said substrate at said first surface portion, a second region of the same conductivity type extending into said substrate at said second surface portion, one of said first and second regions serving as a source region and the other as a drain region of a field effect device in said structure, a thin implanted layer of the opposite conductivity type disposed intermediate said first and second regions, said layer having an upwardly-extending portion that terminates at said slope and serves as a channel region for said device, and a gate electrode disposed overlying at least the portion of said slope that includes the termination of said layer.

Claim 7

The structure of claim 4, further including an insulating layer interposed between said gate electrode and said substrate slope.

Claim 8

The structure of claim 5, wherein said channel and drain regions are spaced apart a distance sufficient to provide a drift region between them.

Claim 9

The structure of claim 4, wherein said implanted layer is provided by ion implantation through an oxide layer formed on said slope, said layer having a thickness that increases progressively from the top to the bottom of the slope.

Claim 10

The structure of claim 4, wherein said first and second regions are of n-type conductivity, and said implanted layer is of p-type conductivity.

Claim 11

The structure of claim 4, wherein said first region serves as the source region, and said channel-forming implanted layer is disposed adjacent said first region.

Claim 12

An integrated circuit structure comprising: a semiconductor substrate having a laterally extending upper surface, said surface including an elevated plateau portion joined by a slope to an adjacent field portion, a first region of one conductivity type in said substrate at least partially underlying said plateau portion of the upper surface, a second region of the same conductivity type in said substrate at least partially underlying said field portion of said surface, one of said first and second regions serving as a source region and the other as a drain region for a field effect device incorporated in said structure, a thin implanted layer of the opposite conductivity type disposed intermediate said first and second regions, said layer having an upwardly extending marginal portion that terminates at said slope and serves as a channel region for said device, an insulating layer covering at least the portion of said slope that includes the termination of said implanted layer, and a gate electrode disposed on said insulating layer overlying said channel region.

Claim 13

An integrated circuit structure comprising: a semiconductor substrate having a laterally extending upper surface, said surface including an elevated plateau portion joined by a slope to an adjacent field portion, a first region of one conductivity type in said substrate at least partially underlying said plateau portion of the upper surface, a second region of the same conductivity type in said substrate at least partially underlying said field portion of said surface, one of said first and second regions serving as a source region and the other as a drain region for a field effect device incorporated in said structure, a thin implanted layer of the opposite conductivity type disposed intermediate said first and second regions, said layer having an upwardly extending marginal portion that terminates at said slope and serves as a channel region for said device, an insulating layer covering at least the portion of said slope that includes the termination of said implanted layer, and a gate electrode disposed on said insulating layer overlying said channel region.