Gate turn-off triac with dual low conductivity regions contacting central gate region

Claim 1

A gate turn-off semiconductor triac device having first and second main terminals and a gate electrode and capable (1) when it is in its high impedance state of blocking voltages applied across its main terminals in either polarity and (2) of being placed in a low impedance state for conducting current in a direction determined by the polarity of the voltage applied across its main terminals, said gate turn-off semiconductor triac device comprising: a body of semiconductor material having first and second major sides; a first region having a first conductivity type; a gate region having a second conductivity type disposed adjacent said first region, said gate region forming a first PN junction with said first region at its interface therewith, said gate region having a higher conductivity than the adjacent portion of said first region; a second region having said first conductivity type disposed adjacent said gate region and forming a second PN junction with said gate region at its interface therewith, the portion of said second region adjacent said gate region having a lower conductivity than said gate region, said second region being spaced apart from said first region by said gate region; a first first-type emitter region having said first conductivity type disposed adjacent said first region and said first major side of said body of semiconductor material, said first first-type emitter region being spaced from said gate region by said first region; a second first-type emitter region having said first conductivity type disposed adjacent said second region and said second major surface of said body of semiconductor material, said second first-type emitter region being spaced from said gate region by said second region; a first second-type emitter region having said second conductivity type disposed adjacent said second region and said second major side of said body of semiconductor material, said first second-type emitter region forming a third PN junction with said second region at its interface therewith, said first second-type emitter region being spaced apart from said gate region by said second region; a second second-type emitter region having said second conductivity type disposed adjacent said first region and said first major side of said body of semiconductor material, said second second-type emitter region forming a fourth PN junction with said first region at its interface therewith, said second second-type emitter region being spaced apart from said gate region by said first region; first main terminal means disposed adjacent said first major side of said body of semiconductor material and contacting said first first-type emitter region and said second second-type emitter region; second main terminal means disposed adjacent said second major side of said body of semiconductor material and contacting said second first-type emitter region and said first second-type emitter region; gate electrode means contacting said gate region; said first second-type emitter region isolated from said gate region by said second and third PN junctions which together constitute a pair of back-to-back PN junctions; said second second-type emitter region isolated from said gate region by said first and fourth PN junctions which together constitute a pair of back-to-back PN junctions; whereby a gate signal of a predetermined polarity can switch said triac from its low impedance state to its high impedance state.