US4213191A
Expired / Lapsed
US
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Variable length delay line
Assignee: Westinghouse Electric Corp
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Filing: 1978-03-16
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Granted: 1980-07-15
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Expires: 1998-03-16
Abstract
Abstract A variable length delay line comprises a random-access-memory (RAM) device in which a selected shift between read and write addresses establishes the desired amount of delay.
Inventors
- 👤 Robert S. Gemp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:29
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F2205/00; G06F2205/10; G06F2205/104
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
In a digital delay line apparatus including a delay line having a plurality of memory locations; and means for addressing said memory locations in a write mode to store therein in a recirculated manner a digital signal and for addressing said memory locations in a read mode to retrieve the stored digital signal; the combination of: free-running counter means for generating a first instantaneous count; said addressing means being responsive to said first instantaneous count as a write address for said memory locations in the write mode for storing said digital signal; and means responsive to said first instantaneous count and to a predetermined count for generating a second instantaneous count, said second instantaneous count differing from said first instantaneous count by said predetermined count; said addressing means being responsive to said second instantaneous count as a read address for said memory locations in the read mode for retrieving said stored digital signal; whereby said digital signal is retrieved with a delay equal to said predetermined count.
Claim 2
Dependent Claim
167 words
In a digital delay line apparatus including a delay line having a plurality of memory locations; and means for addressing said memory locations in a write mode to store therein in a recirculated manner a digital signal and for addressing said memory locations in a read mode to retrieve the stored digital signal; the combination of: free-running counter means for generating a first instantaneous count; said addressing means being responsive to said first instantaneous count as a write address for said memory locations in the write mode for storing said digital signal; and means responsive to said first instantaneous count and to a predetermined count for generating a second instantaneous count, said second instantaneous count differing from said first instantaneous count by said predetermined count; said addressing means being responsive to said second instantaneous count as a read address for said memory locations in the read mode for retrieving said stored digital signal; whereby said digital signal is retrieved with a delay equal to said predetermined count.
Claim 3
Dependent Claim
22 words
The apparatus of claim 1 with said predetermined count being adjustable in relation to a control signal for adjusting said signal delay.
Claim 4
Dependent Claim
17 words
The apparatus of claim 2 with said delay line consisting in at least one random-access-memory (RAM) device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-07-15 | 1984-01-14 | 1984-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-07-15 | 1988-01-14 | 1988-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-07-15 | 1992-01-14 | 1992-07-15 | $7700.00 | Window Closed / Lapsed |