Multi-channel charge coupled transfer device

Claim 1

A charge transfer device comprising: a semiconductor substrate of one conductivity type; an insulation layer formed on said substrate; N charge transfer channels arranged in parallel and having inputs connected to a common input node formed in said substrate and outputs to a common output node formed in said substrate and each channel including P transfer electrodes disposed on said insulating layer in a charge transfer direction, the N corresponding transfer electrodes of the respective charge transfer channels being arranged in the direction normal to the charge transfer direction and being electrically connected together; means for forming a potential barrier in part at the charge incoming side of said semiconductor substrate under each of only M (<P) successive transfer electrodes of each of said N charge transfer channels in response to application of a potential of a storage level to the transfer electrode to form a storage cell under each of said M electrodes of each of said charge transfer channels for storing a signal charge packet, the N sets of said respective M transfer electrodes under which said potential barriers are to be formed being arranged such that the first electrodes of said respective M successive transfer electrodes are successively displaced by one transfer electrode in the charge transfer direction at the input side of said charge transfer channels and the last electrodes of said respective M successive transfer electrodes are successively displaced by one transfer electrode in the charge transfer direction at the output side of said charge transfer channels, and said storage cell being responsive to application of a potential of a transfer level on the associated transfer electrode to receive a signal charge packet from the adjacent preceding cell at the storage level; means for applying N-phase non-overlapping offset clock pulse signals to said transfer electrodes of said N charge transfer channels, said clock pulse signals each being normally biased to the storage level and pulsed to the transfer level in order that N successive transfer electrodes in each of said charge transfer channels are successively set to the transfer level in the direction opposite to the charge transfer direction whereby input data from said input node are sequentially applied to said N transfer channels and parallel data from said charge transfer channels are applied sequentially to said output node by said N-phase clock signals and, in each of said charge transfer channels, a signal charge packet is shifted one storage cell in the charge transfer direction during one cycle period of said N-phase clock pulse signals while an empty storage cell is shifted one cell position in the direction opposite to the charge transfer direction each time a clock signal is pulsed; and, means for forming a fat "O" potential barrier in part at the charge incoming side of said semiconductor substrate under each of transfer electrodes disposed between said input node and the first electrode of said respective M successive transfer electrodes of said charge transfer channels to store a fat "O" charge under the associated transfer electrode.