Electronic speed error signal processing circuit

Claim 2

A signal processor comprising: first channel means for providing a substantially unattenuated output signal in response to error signal fluctuations above a selected threshold level of one polarity regardless of frequency, said first channel means including a first signal threshold generating means operatively connected to a first impedance network with a predetermined time constant; second channel means for providing a substantially unattenutated output signal in response to error signal fluctuations above a selected threshold level of opposite polarity regardless of frequency, said second channel means including a second signal threshold generating means operatively connected to a second impedance network with a predetermined time constant; and third channel means for providing a substantially unattenuated output signal in response to error signal fluctuations below a selected frequency and substantial attenuation to error signal fluctuations above said selected frequency, said third channel means including a third impedance network with a predetermined time constant, said first and second signal threshold generating means comprising a current source supplying current to a first resistor in series with a second resistor of equal value, the juncture between said current source and said first resistor maintaining a negative threshold level with respect to the juncture of said first and second resistors, and the remaining terminal of said second resistor maintaining a positive threshold level with respect to the juncture of said first and second resistors; and said first, second and third channel means including respective inputs operatively coupled together to comprise the input to said signal processor and said first, second and third channel means including respective outputs operatively coupled together to comprise the output of said signal processor.

Claim 3

The signal processor of claim 1 wherein said first channel means includes first ideal diode means for providing said output signal in response to error signal fluctuations of one polarity and said second channel means includes second ideal diode means for providing said output signal in response to error signal fluctuations of opposite polarity.

Claim 4

The signal processor of claim 1 wherein the respective time constants of said first and second impedance networks are substantially equal and substantially less than the time constant of said third impedance network.

Claim 5

A closed loop electric power generating system comprising: an electric power generating means; a fluid driven, inlet valve controlled prime mover operatively connected by a common shaft to said electric power generating means; detecting means responsive to the rotational velocity of said shaft for generating a speed error signal proportional in magnitude to the deviation of actual shaft velocity from desired shaft velocity; a signal processor including: first channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations above a selected threshold level of one polarity regardless of frequency, said first channel means including a first signal threshold generating means operatively coupled to a first impedance network with a predetermined time constant; second channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations above a selected threshold level of opposite polarity regardless of frequency, said second channel means including a second signal threshold generating means operatively coupled to a second impedance network with a predetermined time constant; third channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations below a selected frequency and substantial attenuation to error signal fluctuations above said selected frequency, said third channel means including a third impedance network with a predetermined time constant, said first and second signal threshold generating means comprising a current source supplying current to a first resistor in series with a second resistor of equal value, the juncture between said current source and said first resistor maintaining a negative threshold level with respect to the juncture of said first and second resistors, and the remaining terminal of said second resistor maintaining a positive threshold level with respect to the juncture of said first and second resistors; and valve load control means for opening and closing said inlet valves to control load and shaft velocity in accordance with the output signal from said signal processor.

Claim 6

A closed loop electric power generating system comprising: an electric power generating means; a fluid driven, inlet valve controlled prime mover operatively connected by a common shaft to said electric power generating means; detecting means responsive to the rotational velocity of said shaft for generating a speed error signal proportional in magnitude to the deviation of actual shaft velocity from desired shaft velocity; a signal processor including: first channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations above a selected threshold level of one polarity regardless of frequency, said first channel means including a first signal threshold generating means operatively coupled to a first impedance network with a predetermined time constant; second channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations above a selected threshold level of opposite polarity regardless of frequency, said second channel means including a second signal threshold generating means operatively coupled to a second impedance network with a predetermined time constant; third channel means coupled to said detecting means for providing a substantially unattenuated output signal in response to error signal fluctuations below a selected frequency and substantial attenuation to error signal fluctuations above said selected frequency, said third channel means including a third impedance network with a predetermined time constant, said first and second signal threshold generating means comprising a current source supplying current to a first resistor in series with a second resistor of equal value, the juncture between said current source and said first resistor maintaining a negative threshold level with respect to the juncture of said first and second resistors, and the remaining terminal of said second resistor maintaining a positive threshold level with respect to the juncture of said first and second resistors; and valve load control means for opening and closing said inlet valves to control load and shaft velocity in accordance with the output signal from said signal processor.

Claim 7

The electric power generating system of claim 4 wherein said first channel means includes first ideal diode means for providing said output signal in response to signals of one polarity and said second channel means includes second ideal diode means for providing said output signal in response to signals of opposite polarity.

Claim 8

The electric power generating system of claim 4 wherein the magnitude of the output signal of said current source is variable and controls the threshold levels of said threshold generating means.