Patent US4204261A successfully refreshed from Google Patents.
US4204261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complex analog signal generator
Assignee: Conmed Corp
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Filing: 1978-03-01
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Granted: 1980-05-20
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Expires: 1998-03-01
Abstract
Abstract An electronic circuit for generating complex time-varying analog signal waveforms such as electrocardiogram and blood pressure transducer signals employs analog signal shaping circuits coupled to a summing network to shape the sequential output stage signals of a multiple stage counter and also employs an interface to couple the signal waveforms to external display devices.
Inventors
- 👤 Frederick B. Ruszala
- 👤 Kenneth J. Cook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:30
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/26; A; A61; A61B; A61B5/00; A61B5/02; A61B5/021; A61B5/24; A61B5/316; A61B5/318; A61B5/319; G06G7/48; G06G7/60; H; H03; H03K; H03K6/00
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
160 words
An electronic circuit for generating a simulated complex time-varying biological signal waveform, comprising: counter means having a plurality of stages for sequentially providing a uniform digital output signal to each stage; clock means for regularly advancing the state of the counter wherein said digital signal is exclusively provided to only one stage at a time; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter so that each shaping circuit is sequentially energized by the digital output signal from its corresponding counter stage, said shaping circuits generating segments of a simulated electrocardiogram waveform, with one of said shaping circuits including a resistive-capacitor integrator for shaping the output of one stage of the counter into electrocardiogram P-segment; and summing means connected to the outputs of each of the analog signal shaping circuits whereby the summing means provides a time-varying analog signal simulating an electrocardiogram waveform as its output.
Claim 2
Dependent Claim
160 words
An electronic circuit for generating a simulated complex time-varying biological signal waveform, comprising: counter means having a plurality of stages for sequentially providing a uniform digital output signal to each stage; clock means for regularly advancing the state of the counter wherein said digital signal is exclusively provided to only one stage at a time; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter so that each shaping circuit is sequentially energized by the digital output signal from its corresponding counter stage, said shaping circuits generating segments of a simulated electrocardiogram waveform, with one of said shaping circuits including a resistive-capacitor integrator for shaping the output of one stage of the counter into electrocardiogram P-segment; and summing means connected to the outputs of each of the analog signal shaping circuits whereby the summing means provides a time-varying analog signal simulating an electrocardiogram waveform as its output.
Claim 3
Dependent Claim
16 words
The electronic circuit of claim 1 wherein the simulated biological waveform is a blood pressure waveform.
Claim 4
Dependent Claim
50 words
The electronic circuit of claim 1 wherein one of said signal shaping circuits shapes an output of said counter into a Q segment of said electrocardiogram waveform and comprises: a resistive-capacitive integrator having an input and an output; and an inverting amplifier connected to the output of said resistive-capacitive integrator.
Claim 5
Dependent Claim
63 words
The electronic circuit of claim 1 wherein one of said analog signal shaping circuits shapes an output of said counter into an R segment of an electrocardiogram waveform and comprises: a resistive-capacitive differentiator having an input and an output; a unidirectional conductive means connected to the output of said resistive-capacitive differentiator; and a resistive-capacitive integrator connected to the output of said resistive-capacitive differentiator.
Claim 6
Dependent Claim
54 words
The electronic circuit of claim 1 wherein one of said analog signal shaping circuits shapes an output of said counter into the S segment of an electrocardiogram waveform and comprises: a resistive-capacitive integrator having an input and an output; and an inverting amplifier having an input connected to the output of said resistive-capacitive integrator.
Claim 7
Dependent Claim
41 words
The electronic circuit of claim 1 wherein one of said analog signal shaping circuits shapes at least two outputs of said counter into the T segment of an electrocardiogram waveform and comprises: a resistive-capacitive integrator having two inputs and one output.
Claim 8
Dependent Claim
31 words
The electronic circuit of claim 1 wherein the summing means comprises: a plurality of resistors having a common node connected to the output of each of said analog signal shaping circuits.
Claim 9
Dependent Claim
73 words
The electronic circuit of claim 1 wherein said clock means includes oscillator means for providing a plurality of clock signals to said counter, said oscillator means having a disenable input for preventing generation of said clock signals and wherein said circuit further comprises: means for providing a disabling signal to the disenable input of said oscillator for temporarily preventing further generation of the clock signals thereby defining discrete periods for the generated waveforms.
Claim 10
Dependent Claim
88 words
The electronic circuit of claim 8 which further includes: monostable means coupled between the last stage of the counter and the disenable input of the oscillator, with said monostable means being triggered upon receipt of a signal from the last stage and providing a signal of a given duration to said oscillator to inhibit operation thereof; and adjustable resistive-capacitive means coupled to said monostable means for controlling the duration of its output signal whereby the period of the waveform may be changed by adjustment of said resistive-capacitive means.
Claim 11
Dependent Claim
76 words
The electronic circuit of claim 1 which further comprises: second counter means having a plurality of states for sequentially providing a uniform digital output signal to each stage; a second plurality of analog signal shaping circuits each coupled to a stage counter for generating a simulated blood pressure waveform; and means for coupling the output of the block means to said second counter so that the simulated electrocardiogram and blood pressure waveforms are generated in synchronization.
Claim 12
Dependent Claim
41 words
The electronic circuit of claim 10 wherein one of the analog signal shaping circuits for shaping the blood pressure waveform comprises: an inverter coupled to the output of one stage, with the output of the inverter being connected to a resistor.
Claim 13
Dependent Claim
22 words
The electronic circuit of claim 11 wherein the other analog signal shaping circuits for generating the blood pressure waveform comprise resistive networks.
Claim 14
Dependent Claim
33 words
The electronic circuit of claim 12 wherein the outputs of all of the analog signal shaping circuits for generating the blood pressure waveform are summed together and then shaped by a resistive-capacitive network.
Claim 15
Dependent Claim
27 words
The electronic circuit of claim 10 which further comprises: means coupled to the last output stage of the first counter for resetting said first and second counters.
Claim 16
Dependent Claim
57 words
The electronic circuit of claim 14 wherein said reset means comprises: monostable means for generating a signal of a given duration upon receipt of a triggering signal from the last counter output stage, said monostable signal being coupled to a reset input of said first and second counters, and to a disabling input of the clock means.
Claim 17
Dependent Claim
199 words
An electronic circuit for generating a simulated electrocardiogram waveform, comprising: multistage counter means for sequentially providing an output signal at each stage; a plurality of analog signal shaping circuits each coupled to a stage of the counter, said shaping circuits including: a resisitive-capacitive integrator to form a P segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having an input and output, and an inverting amplifier connected to the output of said resistive-capacitive integrator to form a Q segment of said simulated electrocardiogram waveform; a resisitive-capacitive differentiator having an input and an output, a unidirectional conductive means connected to the output of said resistive-capacitive differentiator, and a resistive-capacitive integrator connected to the output of said resistive-capacitive differentiator to form an R segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having an input and an output, and an inverting amplifier having an input connected to the output of said resistive-capacitive integrator to form an S segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having two inputs and one output to form a T segment of said simulated electrocardiogram waveform; and means for summing the outputs of the analog signal shaping circuits to provide a completed simulated electrocardiogram waveform.
Claim 18
Dependent Claim
199 words
An electronic circuit for generating a simulated electrocardiogram waveform, comprising: multistage counter means for sequentially providing an output signal at each stage; a plurality of analog signal shaping circuits each coupled to a stage of the counter, said shaping circuits including: a resisitive-capacitive integrator to form a P segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having an input and output, and an inverting amplifier connected to the output of said resistive-capacitive integrator to form a Q segment of said simulated electrocardiogram waveform; a resisitive-capacitive differentiator having an input and an output, a unidirectional conductive means connected to the output of said resistive-capacitive differentiator, and a resistive-capacitive integrator connected to the output of said resistive-capacitive differentiator to form an R segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having an input and an output, and an inverting amplifier having an input connected to the output of said resistive-capacitive integrator to form an S segment of said simulated electrocardiogram waveform; a resistive-capacitive integrator having two inputs and one output to form a T segment of said simulated electrocardiogram waveform; and means for summing the outputs of the analog signal shaping circuits to provide a completed simulated electrocardiogram waveform.
Claim 19
Dependent Claim
122 words
An electronic circuit for generating a simulated time-varying signal waveform to test the operation of a remote device, comprising: a counter having a plurality of stages; means for regularly advancing the stage of the counter; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter; summing means connected to the outputs of each of the analog signal shaping circuits whereby the summing means provides a simulated time-varying analog signal waveform as its output; and an interface connected between said summing means and the remote device operative to thereby modulate a carrier frequency signal received from the remote device with said time-varying signal waveform for transmission to the remote device.
Claim 20
Dependent Claim
122 words
An electronic circuit for generating a simulated time-varying signal waveform to test the operation of a remote device, comprising: a counter having a plurality of stages; means for regularly advancing the stage of the counter; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter; summing means connected to the outputs of each of the analog signal shaping circuits whereby the summing means provides a simulated time-varying analog signal waveform as its output; and an interface connected between said summing means and the remote device operative to thereby modulate a carrier frequency signal received from the remote device with said time-varying signal waveform for transmission to the remote device.
Claim 21
Dependent Claim
43 words
The electronic circuit of claim 17 wherein said interface comprises: analog switch means operative to modulate said carrier frequency signal with said time-varying signal waveform; and power supply means operative to rectify said carrier frequency signal and thereby power said analog switch means.
Claim 22
Dependent Claim
137 words
An electronic circuit for generating a simulated waveform for testing a remote device, comprising: a counter having a plurality of stages; means for regularly advancing the stage of the counter; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter; summing means connected to the outputs of each of the analog signal shaping circuits whereby summing means provides a simulated time-varying analog signal waveform as its output; a divider network coupled to the summing means and having a plurality of resistive legs for supplying said simulated signal at selected levels to the remote device; and calibration means connected to the summing means operative to generate a reference signal at the output of a selected resistive leg pair wherein said remote device may be calibrated.
Claim 23
Dependent Claim
137 words
An electronic circuit for generating a simulated waveform for testing a remote device, comprising: a counter having a plurality of stages; means for regularly advancing the stage of the counter; a plurality of analog signal shaping circuits each having an input and output, with each input connected to a stage of the counter; summing means connected to the outputs of each of the analog signal shaping circuits whereby summing means provides a simulated time-varying analog signal waveform as its output; a divider network coupled to the summing means and having a plurality of resistive legs for supplying said simulated signal at selected levels to the remote device; and calibration means connected to the summing means operative to generate a reference signal at the output of a selected resistive leg pair wherein said remote device may be calibrated.
Claim 24
Dependent Claim
108 words
In a biological waveform simulator device, an electronic circuit for modulating a carrier frequency signal with an information containing signal for transmission to a remote device, comprising: analog switch means having two signal inputs and a power supply input for energizing components thereof, said switch means operative to amplitude modulate said carrier frequency signal on one input with said information signal on the other input wherein the amplitude modulated signal is transmitted to the remote device; and power supply means operative to rectify said carrier frequency signal and coupling the rectified output to the power supply input of the switch means to thereby power said analog switch means.
Claim 25
Dependent Claim
108 words
In a biological waveform simulator device, an electronic circuit for modulating a carrier frequency signal with an information containing signal for transmission to a remote device, comprising: analog switch means having two signal inputs and a power supply input for energizing components thereof, said switch means operative to amplitude modulate said carrier frequency signal on one input with said information signal on the other input wherein the amplitude modulated signal is transmitted to the remote device; and power supply means operative to rectify said carrier frequency signal and coupling the rectified output to the power supply input of the switch means to thereby power said analog switch means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-05-20 | 1983-11-19 | 1984-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-05-20 | 1987-11-19 | 1988-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-05-20 | 1991-11-19 | 1992-05-20 | $7700.00 | Window Closed / Lapsed |