Catapult breakaway load simulator circuit

Claim 1

A circuit for developing a required load vs. time signal to simulate the breakaway fitting load during a typical catapult launch comprising: a. means for providing a clock pulse signal, said signal having a first amplitude, b. means connected to said clock signal providing means for generating a first driver signal, said first driver signal being said first amplitude for a time period equal to seven cycles of said clock pulse signal followed by a second amplitude for a time period equal to one cycle of said clock pulse signal, said first amplitude being greater in value than that said second value, said first driver signal repeating once every eight cycles of said clock signal, c. means connected to said first driver signal generating means for generating a first summing signal, said first summing signal being a ramp function starting at said second amplitude and terminating at a third amplitude with a time period equal to four cycles of said clock signal, followed by said third amplitude for a time period equal to three cycles of said clock signal, followed by said second amplitude for a time period equal to one cycle of said clock signal, said third amplitude being less than said first amplitude but greater than said second amplitude, said first summing signal repeating once every eight cycles of said clock signal, d. means connected to said first driver signal generating means for generating a second driver signal, said second driver signal being said second amplitude for a time period of seven cycles of said clock signal followed by said first amplitude for a time period of less than one cycle of said clock signal, followed by said second amplitude for the remainder of the eights cycle of said clock signal a time period of less than one cycle of said clock signal, said second driver signal repeating once every eight cycles of said clock signal, e. means connected to said second driver signal generating means for generating a second summing signal, said second summing signal being said second amplitude for a time period equal to seven cycles of said clock signal, followed by a spike pulse signal of amplitude equal to said first amplitude for a time period of less than one cycle, followed by said second amplitude for a time period of less than one cycle, said second summing signal repeating once every eight cycles of said clock signal, f. means connected to said second driver signal generating means for generating a third summing signal, said third summing signal being said second amplitude for a time period equal to more than seven cycles of said clock signal but less than eight cycles of said clock signal followed by a fourth amplitude for a time period equal to less than one cycle of said clock signal, said fourth amplitude being less than said second amplitude, said third summing signal repeating once every eighth cycle of said clock signal, and g. summing means connected to said first, second, and third summing signal generator means for summing said first, second, and third summing signals, said summing means having an output upon which appears said load vs. time signal, said load vs. time signal repeating once every eight cycles of said clock signal.