Data conversion system

Claim 2

A data conversion method comprising the steps of generating a repetitive clock signal having first and second phases of a predetermined amplitude, representing a series of binary digits through actuation of a series of switching means each having a first condition corresponding to one binary situation and a second condition corresponding to the other binary situation, inputting said clock signal to a counting means to produce a plurality of timing signals, and inputting said plurality of timing signals to said series of switching means to produce a data signal, generating an output signal by combining said clock signal and said data signal, and transmitting said output signal through use of a communication means.

Claim 3

The method according to claim 1 wherein transmitting said output signal includes recording said output signal.

Claim 4

The method according to claim 1 wherein inputting said plurality of timing signals to said series of switching means includes individually inputting each of said plurality of timing signals to an input of each of said series of switching means, connecting an output of each of said series of switching means to a common output whereby said data signal is produced at said common output.

Claim 5

The method according to claim 3 wherein generating said output signal includes limiting said data signal through use of a bilateral switch means to produce a limited output with said clock signal.

Claim 6

The method according to claim 3 further including receiving said output signal after transmission, combining said output signal with a second plurality of outputs of a second counting means, detecting relative amplitudes of the second plurality of outputs of said second counting means with level detector means, and combining said second plurality of outputs of said second counting means with an output of said level detector means through a third plurality of gating means.

Claim 7

The method according to claim 5 wherein detecting relative amplitudes of said second plurality of outputs of said second counting means includes equating a first amplitude level of said output signals with one binary situation and equating a second amplitude level of said output signals with the other binary situation.

Claim 8

A data conversion system comprising: clock means for generating a repetitive bipolar square wave clock signal; first counter means for generating a repetitive first plurality of outputs in response to said clock signal; a series of manually selectable switch means for indicating one of a first and a second binary situation; said series of switch means connected in electrical parallel with said first counter means, said first plurality of outputs of said first counter means generating a second plurality of outputs of said series of switch means, modulation means for generating an output signal, said modulation means combining said second plurality of outputs of said series of switch means and said clock signal, and communication means for preserving said output signal.

Claim 9

A data conversion system comprising: clock means for generating a repetitive bipolar square wave clock signal; first counter means for generating a repetitive first plurality of outputs in response to said clock signal; a series of manually selectable switch means for indicating one of a first and a second binary situation; said series of switch means connected in electrical parallel with said first counter means, said first plurality of outputs of said first counter means generating a second plurality of outputs of said series of switch means, modulation means for generating an output signal, said modulation means combining said second plurality of outputs of said series of switch means and said clock signal, and communication means for preserving said output signal.

Claim 10

The data conversion system according to claim 7 wherein said first situation indicated by said series of switch means corresponds to the presence of a binary information bit and said second binary situation indicated by said series of switch means corresponds to the absence of the binary information bit.

Claim 11

The data conversion system according to claim 8 wherein said modulation means includes detector means for sensing the relative amplitude of said output signal, and limiting means for altering the magnitude of said clock signal whenever said detector means senses said second binary situation.

Claim 12

A data conversion system comprising a generation portion, a communication portion, and a receiving portion, said generation portion including clock means for generating a repetitive clock signal having first and second phases of a predetermined amplitude, first counter means for generating a first plurality of outputs in response to said clock signal, a series of switching means for indicating a series of binary digits having a first condition corresponding to one binary situation and a second condition corresponding to the other binary situation, said series of switch means combining said first plurality of outputs of said first counter means to provide a switch output, modulation means for combining said switch output and said clock signal to provide an output signal; said communication portion preserving the output signal for said receiving portion; and, said receiving portion including second counter means for producing a second plurality of outputs, detector means for detecting one of said first and second binary situations in said output signal, a third plurality of gate means for combining the second plurality of outputs from said second counter means and an output of said detector means, said third plurality of gate means providing an output representing binary digits each having a first condition corresponding to one binary situation and a second condition corresponding to the other binary situation.

Claim 13

A data conversion system comprising a generation portion, a communication portion, and a receiving portion, said generation portion including clock means for generating a repetitive clock signal having first and second phases of a predetermined amplitude, first counter means for generating a first plurality of outputs in response to said clock signal, a series of switching means for indicating a series of binary digits having a first condition corresponding to one binary situation and a second condition corresponding to the other binary situation, said series of switch means combining said first plurality of outputs of said first counter means to provide a switch output, modulation means for combining said switch output and said clock signal to provide an output signal; said communication portion preserving the output signal for said receiving portion; and, said receiving portion including second counter means for producing a second plurality of outputs, detector means for detecting one of said first and second binary situations in said output signal, a third plurality of gate means for combining the second plurality of outputs from said second counter means and an output of said detector means, said third plurality of gate means providing an output representing binary digits each having a first condition corresponding to one binary situation and a second condition corresponding to the other binary situation.

Claim 14

The data conversion system according to claim 10 wherein said detector means includes threshold level means for indicating at least one relative amplitude of said output signal wherein said relative level corresponds to one of said first and second binary situations.