Patent US4200969A successfully refreshed from Google Patents.
US4200969A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with multi-layered metalizations
Assignee: Toshiba Corp
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Filing: 1977-09-09
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Granted: 1980-05-06
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Expires: 1997-09-09
Abstract
Abstract There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.
Inventors
- 👤 Masaharu Aoyama
- 👤 Shunichi Hiraki
- 👤 Toshio Yonezawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/60; H10P50/66; H10P50/663; H10P50/667; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49156
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
245 words
A process for fabricating a semiconductor device with multi-layered metalizations comprising the steps of: preparing a semiconductor body; forming on the major surface of said semiconductor body a first insulating layer with first contact holes arranged in a predetermined pattern; forming a first metal layer on said first insulating layer, said first metal layer contacting the major surface of said semiconductor body through said first contact holes; coating a second metal layer onto said first metal layer, said first metal layer having a lower etching rate than the etching rate of said second metal layer, said first and second metal layuers constituting a first conductive member; forming a mask layer with a predetermined pattern on said first conductive member; combining into a single etching means suitable etchants for each of said first metal layer and said second metal layer in concentrations selected from a wide range of useable and workable alternative combinations; etching said first conductive member by etching means and by using said mask layer as a mask to remove unnecessary portions thereof so that said first conductive member has the side wall portions diverged to widen toward said semiconductor body; removing said mask layer; forming on said first conductive member a second insulating layer with second contact holes in a predetermined pattern; forming a second conductive member including at least one metal layer on said second insulating layer, said second conductive member contacting with said first conductive member through said second contact holes.
Claim 2
Dependent Claim
245 words
A process for fabricating a semiconductor device with multi-layered metalizations comprising the steps of: preparing a semiconductor body; forming on the major surface of said semiconductor body a first insulating layer with first contact holes arranged in a predetermined pattern; forming a first metal layer on said first insulating layer, said first metal layer contacting the major surface of said semiconductor body through said first contact holes; coating a second metal layer onto said first metal layer, said first metal layer having a lower etching rate than the etching rate of said second metal layer, said first and second metal layuers constituting a first conductive member; forming a mask layer with a predetermined pattern on said first conductive member; combining into a single etching means suitable etchants for each of said first metal layer and said second metal layer in concentrations selected from a wide range of useable and workable alternative combinations; etching said first conductive member by etching means and by using said mask layer as a mask to remove unnecessary portions thereof so that said first conductive member has the side wall portions diverged to widen toward said semiconductor body; removing said mask layer; forming on said first conductive member a second insulating layer with second contact holes in a predetermined pattern; forming a second conductive member including at least one metal layer on said second insulating layer, said second conductive member contacting with said first conductive member through said second contact holes.
Claim 3
Dependent Claim
24 words
A process according to claim 1, further comprising the step of removing said second metal layer, after the step of removing said mask layer.
Claim 4
Dependent Claim
22 words
A process according to claim 2, in which said removing step of said second metal layers is performed by using plasma-etching method.
Claim 5
Dependent Claim
19 words
A process according to claim 1, in which said first and second conductive members are formed by evaporation method.
Claim 6
Dependent Claim
19 words
A process according to claim 1, in which said first and second conductive members are formed by sputtering method.
Claim 7
Dependent Claim
60 words
A process according to claim 1, in which said second conductive member includes at least third and fourth metal layers, said third metal layer being layered on said second insulating layer and said fourth metal layer being layered on said third metal layer, the etching rate of said third metal layer being lower than that of said fourth metal layer.
Claim 8
Dependent Claim
21 words
A process according to claim 6, further comprising the step of removing said fourth metal layer of said second conductive layer.
Claim 9
Dependent Claim
21 words
A process according to claim 5, in which said removing step of said second conductive member is performed by plasma-etching method.
Claim 10
Dependent Claim
14 words
A process according to claim 1, in which said masking layer is a photoresist.
Claim 11
Dependent Claim
15 words
A process according to claim 1, in which said an etching means is etching solution.
Claim 12
Dependent Claim
42 words
A process according to claim 1, in which said first metal layer is made of aluminum, said second metal layer is made of molybdenum, and said etching means is a compound solution composed of phosphoric acid, acetic acid, nitric acid and water.
Claim 13
Dependent Claim
251 words
A process for fabricating a semiconductor device with multi-layered metalizations comprising the steps of: preparing a semiconductor body; forming on the major surfaces of said semiconductor body a first insulating layer with first contact holes arranged in a predetermined pattern; forming a first metal layer on said first insulating layer, said first metal layer contacting the major surface of said semiconductor body through said first contact holes; coating a second metal layer onto said first metal layer, said first metal layer having a lower etching rate than the etching rate of said second metal layer, said first and second metal layers constituting a first conductive member; forming a mask layer with a predetermined pattern on said first conductive member; combining into a single etching means suitable etchants for each of said first metal layer and said second metal layer, in concentrations selected from a wide range of useable and workable alternative combinations; etching said first conductive member by said etching means and by using said mask layer as a mask to remove unnecessary portions thereof so that said first conductive member has the sidewall portions diverged to widen toward said semiconductor body; removing said mask layer; removing said second metal layer; forming on said first metal layer a second insulating layer with second contact holes in a predetermined pattern; and forming a second conductive member including at least one metal layer on said second insulating layer, said second conductive member contacting with said first metal layer through said second contact holes.
Claim 14
Dependent Claim
251 words
A process for fabricating a semiconductor device with multi-layered metalizations comprising the steps of: preparing a semiconductor body; forming on the major surfaces of said semiconductor body a first insulating layer with first contact holes arranged in a predetermined pattern; forming a first metal layer on said first insulating layer, said first metal layer contacting the major surface of said semiconductor body through said first contact holes; coating a second metal layer onto said first metal layer, said first metal layer having a lower etching rate than the etching rate of said second metal layer, said first and second metal layers constituting a first conductive member; forming a mask layer with a predetermined pattern on said first conductive member; combining into a single etching means suitable etchants for each of said first metal layer and said second metal layer, in concentrations selected from a wide range of useable and workable alternative combinations; etching said first conductive member by said etching means and by using said mask layer as a mask to remove unnecessary portions thereof so that said first conductive member has the sidewall portions diverged to widen toward said semiconductor body; removing said mask layer; removing said second metal layer; forming on said first metal layer a second insulating layer with second contact holes in a predetermined pattern; and forming a second conductive member including at least one metal layer on said second insulating layer, said second conductive member contacting with said first metal layer through said second contact holes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-05-06 | 1983-11-05 | 1984-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-05-06 | 1987-11-05 | 1988-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-05-06 | 1991-11-05 | 1992-05-06 | $7700.00 | Window Closed / Lapsed |