MNOS memory device

Claim 1

A process for forming a semiconductor device comprising the steps of: providing a semiconductor body of N-type conductivity and having a common boundary surface; forming P-type drain and source regions in the semiconductor body, the drain and source regions sharing the common boundary surface with the semiconductor body and defining a channel region located solely therebetween; depositing masking oxide on the common boundary surface to cover the drain, source and channel regions; etching an opening in the masking oxide to expose only a portion of the common boundary surface at the channel region spaced apart from both the source and drain regions; depositing a thin gate oxide layer on the exposed common boundary surface at the channel region; implanting N-type conductivity modifiers into the channel region through the gate oxide layer and forming a doped region aligned with the opening; depositing a layer of insulating material over both the masking oxide and the gate oxide; etching contact openings through the insulator and masking oxide layers to expose the drain and source regions; depositing conductive leads in the contact openings in ohmic contact with the drain and source regions; and providing a conductive head over the thin gate oxide layer to form a gate member.