Conduction through sensing and inverter protection system

Claim 2

An inverter control system for a line commutated inverter having a plurality of legs with gate controlled semiconductor means in each leg for controlling conduction therethrough, comprising: (a) gate pulse generator means for providing gate control signals to each semiconductor means to initiate conduction at a prescribed time, each leg having an interval during which conduction occurs in normal operation and a forbidden interval during which conduction should not occur; (b) a conduction sensor for each leg for detecting conduction therethrough and providing a signal representative of conduction in that leg; (c) circuit means for receiving the signal representative of conduction for each leg and determining when conduction occurs in a leg during a forbidden interval; and, (d) control means responsive to a signal from said circuit means indicating conduction during a forbidden interval for advancing the gate control signals for at least the next two gate control signals so that they occur immediately following the detection of conduction in a forbidden interval.

Claim 3

An inverter control system for a line commutated inverter having a plurality of legs with thyristor means in each leg for controlling conduction therethrough, comprising: (a) a gate pulse generator for providing gating control signals to each thyristor means to gate said thyristor means on and initiate conduction through each respective leg at a prescribed time, each leg having an interval during which conduction occurs in normal operation and a forbidden interval during which conduction should not occur; (b) a forbidden interval signal generator means receiving a timing signal from said gate pulse generator and responsive thereto for providing for each leg a first signal representing the forbidden interval; (c) a conduction sensor for each leg for detecting conduction through the thyristor means therein and providing for each leg a second signal representative of conduction in that leg; (d) circuit means for receiving said first and second signals and providing for each leg a third signal with conduction in the forbidden interval representative of a conduction-through fault; and, (e) control means responsive to said third signal for advancing the gating control signals from the gate pulse generator for at least the next two gate pulses to commutate said fault.

Claim 4

An inverter control system for a line commutated inverter having a plurality of legs with thyristor means in each leg for controlling conduction therethrough, comprising: (a) a gate pulse generator for providing gating control signals to each thyristor means to gate said thyristor means on and initiate conduction through each respective leg at a prescribed time, each leg having an interval during which conduction occurs in normal operation and a forbidden interval during which conduction should not occur; (b) a forbidden interval signal generator means receiving a timing signal from said gate pulse generator and responsive thereto for providing for each leg a first signal representing the forbidden interval; (c) a conduction sensor for each leg for detecting conduction through the thyristor means therein and providing for each leg a second signal representative of conduction in that leg; (d) circuit means for receiving said first and second signals and providing for each leg a third signal with conduction in the forbidden interval representative of a conduction-through fault; and, (e) control means responsive to said third signal for advancing the gating control signals from the gate pulse generator for at least the next two gate pulses to commutate said fault.

Claim 5

An inverter control system as defined in claim 2 in which said control means advances the next two gating pulses to take place as soon as conduction in a forbidden interval is detected, said advance not to exceed a limit of 60°.

Claim 6

An inverter control system as defined in claim 3 in which said control means advances the next succeeding three to five gating pulses by an amount not to exceed 120°, and then returns to normal operation.

Claim 7

An inverter control system as defined in any one of claims 2, 3 or 4 and further comprising a line-to-line voltage sensor connected on the AC side of the inverter to derive a signal representing voltage, and circuit means receiving said signal from said voltage sensor and determining therefrom if sufficient volt-seconds are available to commutate the fault at the time it is detected.

Claim 8

An inverter control system as defined in any one of claims 2, 3 or 4 and further comprising means responsive to said third signal for inhibiting automatic current control systems until the fault is corrected and normal operation restored.

Claim 9

An inverter control system as defined in any one of claims 2, 3 or 4 and further comprising: (a) a current pair sensor for each pair of legs responsive to a mode 1 fault current through the respective pair to provide a mode 1 fault current signal; and, (b) means responsive to said mode 1 fault current signal indicating a mode 1 fault has existed for a predetermined time to shut down said inverter.

Claim 10

An inverter control system as defined in claim 3 in which said advance is to 60°.

Claim 11

An inverter control system as defined in claim 4 in which said next three to five gating pulses are advanced to 120°.