Polyphase inverter system having fault protection and output amplitude regulation through pulse width modulation

Claim 2

In a polyphase inverter system having a plurality of switch means coupled to a DC source for providing a plurality of output signals at a fundamental frequency, the output signals being phase displaced relative to one another, having a constant phase displacement relative to a fixed phase reference and having a succession of half cycles with each half cycle comprising a pair of pulses of substantially equal width, the combination comprising: gating means coupled to the plurality of switch means for selectively opening and closing the switch means for selected periods of time to produce the pairs of pulses; and means associated with the gating means for varying the selected time periods of opening and closing the switch means to produce variations in the widths of the pairs of pulses while at the same time maintaining the phase displacement of the output signals relative to the phase reference constant.

Claim 3

The combination defined in claim 1 above, wherein the means for varying the selected time periods shifts the time positions of both the leading and trailing edges of each pulse toward and away from one another by substantially equal amounts.

Claim 4

The combination defined in claim 1 above, wherein the gating means includes means for generating a clock signal which is fixed in phase relative to the phase reference and which has a frequency which is a multiple of the fundamental frequency, and means responsive to the clock signal for successively generating pairs of gating pulses, each pair of gating pulses being equidistant in time from the time center of a different cycle of the clock signal, and wherein the means for varying the selected time periods includes means associated with the gating pulse pair generating means for selectively varying the time positions of each pair of gating pulses relative to the time center of the associated clock signal cycle.

Claim 5

The combination defined in claim 3 above, wherein the means for varying the selected time periods includes means for generating a signal of ramp waveform which is symmetrical relative to a reference axis, means responsive to a dwell angle command signal for generating a pair of error signals which are of equal value and of opposite sense relative to the reference axis, and means responsive to the signal of ramp waveform and the pair of error signals and associated with the gating pulse pair generating means for controlling the time positions of each generated pair of pulses in accordance with the time positions at which the pair of error signals are equal in value to the signal of ramp waveform.

Claim 6

A polyphase inverter system for generating a plurality of output signals of fundamental frequency which are displaced in phase relative to one another and to a phase reference, comprising: a DC source; a plurality of switching means coupled to the DC source; means for generating a clock signal having a frequency at a multiple of the fundamental frequency; means responsive to the clock signal for generating a succession of gating signals in synchronism therewith; means responsive to the gating signals for operating the switching means to produce a plurality of pulses during each half cycle of the fundamental frequency, said means including counter means responsive to the clock signal for generating a staggered succession of timing signals and gate matrix means responsive to the timing signals and to the gating signals for gating selected ones of the gating signals to the switching means under the control of the timing signals; and means associated with the means for generating a succession of gating signals for selectively varying the time positions of the gating signals to vary the width of each of the plurality of pulses by symmetrically displacing the leading and trailing edges of each pulse relative to the pulse center by substantially equal amounts.

Claim 7

A polyphase inverter system for generating a plurality of output signals of fundamental frequency which are displaced in phase relative to one another and to a phase reference, comprising: a DC source; a plurality of switching means coupled to the DC source; means for generating a clock signal having a frequency at a multiple of the fundamental frequency; means responsive to the clock signal for generating a succession of gating signals in synchronism therewith; means responsive to the gating signals for operating the switching means to produce a plurality of pulses during each half cycle of the fundamental frequency, said means including counter means responsive to the clock signal for generating a staggered succession of timing signals and gate matrix means responsive to the timing signals and to the gating signals for gating selected ones of the gating signals to the switching means under the control of the timing signals; and means associated with the means for generating a succession of gating signals for selectively varying the time positions of the gating signals to vary the width of each of the plurality of pulses by symmetrically displacing the leading and trailing edges of each pulse relative to the pulse center by substantially equal amounts.

Claim 8

A polyphase inverter system in accordance with claim 5, wherein the means for generating a succession of gating signals includes means for generating a feedback signal of the fundamental frequency and of selected phase relative to the phase reference, and further including means for receiving an external reference signal having a frequency determining the fundamental frequency and a phase determining the phase reference, and means responsive to the feedback and reference signals and coupled to the clock signal generating means for adjusting the frequency and phase of the clock signal in accordance with a comparison of the frequency and phase of the feedback and reference signals.

Claim 9

A polyphase inverter system in accordance with claim 5, wherein the means for selectively varying the time positions of the gating signals responds to the amplitude of the output signals to cause the width of each of the plurality of pulses to vary as a linear function of the amplitude of the output signals.

Claim 10

A polyphase inverter system in accordance with claim 7, further including means for adding to the gating pulses a separate set of gating pulses at selected time positions independently of the means for selectively varying the time positions of the gating pulses whenever the amplitude of the output signals exceeds a threshold value, the separate set of gating pulses effecting a substantially instantaneous change in the widths of the plurality of pulses.

Claim 11

An inverter system for generating a three-phase output in synchronism with a reference signal defining a fundamental frequency and a phase reference, the three-phase output comprising three-phase displaced signals of the fundamental frequency havIng phases which are fixedly related to the phase reference and generally sinusoidal waveforms, comprising the combination of: a DC source; a plurality of inverter bridge means coupled to the DC source and each including a plurality of switching means; transformer means coupled to the plurality of inverter bridge means for providing the three output signals; first clock means for generating a first clock signal having a frequency which is a multiple of the fundamental frequency; second clock means responsive to the first clock means for generating a second clock signal having a frequency which is a submultiple of the frequency of the first clock signal; means for providing an amplitude reference signal; error circuit means responsive to the amplitude reference signal and to the amplitude of the output signals for generating an error signal in accordance with the difference therebetween; dwell control means responsive to the first clock signal and to the error signal for generating a pair of signal indications within each cycle of the first clock signal, each pair of signal indications being disposed substantially equidistant from and on opposite sides of the center of the interval defined by the associated cycle of the first clock signal, the distances between the signal indications and the interval center being varied in direct relation to the value of the error signal; separate gating circuit means coupling each of the inverter bridge means to the second clock means for operating the switching means of the associated inverter bridge means to produce a separate pair of pulses in each half cycle of each of the three output signal phases at the transformer means, each gating circuit means including counter means responsive to the second clock signal to provide successive enabling signals during the different successive cycles of the second clock signal, the counter means including means responsive to the successive enabling signals for generating a feedback signal of the fundamental frequency therefrom, gate pulse timer means responsive to the second clock signal and to the signal indications from the dwell control means for generating a gating pulse in time coincidence with each signal indication, the gate pulse timer means including bistable means changing state in response to each gating pulse to provide an inhibit signal, plural driver means, each coupled to operate a different one of the plurality of switching means in the associated inverter bridge means in response to a gate drive signal, and logic means responsive to the enabling signals, the inhibit signal and the gating pulses for providing the gate drive signals to the associated driver means in accordance with a predetermined logic scheme; and means responsive to the reference signal and to the feedback signal from the countermeans of one of the gating circuit means and coupled to the first clock means for regulating the frequency and phase of the first clock signal in accordance with any differences between the reference and feedback signals.

Claim 12

An inverter system for generating a three-phase output in synchronism with a reference signal defining a fundamental frequency and a phase reference, the three-phase output comprising three-phase displaced signals of the fundamental frequency havIng phases which are fixedly related to the phase reference and generally sinusoidal waveforms, comprising the combination of: a DC source; a plurality of inverter bridge means coupled to the DC source and each including a plurality of switching means; transformer means coupled to the plurality of inverter bridge means for providing the three output signals; first clock means for generating a first clock signal having a frequency which is a multiple of the fundamental frequency; second clock means responsive to the first clock means for generating a second clock signal having a frequency which is a submultiple of the frequency of the first clock signal; means for providing an amplitude reference signal; error circuit means responsive to the amplitude reference signal and to the amplitude of the output signals for generating an error signal in accordance with the difference therebetween; dwell control means responsive to the first clock signal and to the error signal for generating a pair of signal indications within each cycle of the first clock signal, each pair of signal indications being disposed substantially equidistant from and on opposite sides of the center of the interval defined by the associated cycle of the first clock signal, the distances between the signal indications and the interval center being varied in direct relation to the value of the error signal; separate gating circuit means coupling each of the inverter bridge means to the second clock means for operating the switching means of the associated inverter bridge means to produce a separate pair of pulses in each half cycle of each of the three output signal phases at the transformer means, each gating circuit means including counter means responsive to the second clock signal to provide successive enabling signals during the different successive cycles of the second clock signal, the counter means including means responsive to the successive enabling signals for generating a feedback signal of the fundamental frequency therefrom, gate pulse timer means responsive to the second clock signal and to the signal indications from the dwell control means for generating a gating pulse in time coincidence with each signal indication, the gate pulse timer means including bistable means changing state in response to each gating pulse to provide an inhibit signal, plural driver means, each coupled to operate a different one of the plurality of switching means in the associated inverter bridge means in response to a gate drive signal, and logic means responsive to the enabling signals, the inhibit signal and the gating pulses for providing the gate drive signals to the associated driver means in accordance with a predetermined logic scheme; and means responsive to the reference signal and to the feedback signal from the countermeans of one of the gating circuit means and coupled to the first clock means for regulating the frequency and phase of the first clock signal in accordance with any differences between the reference and feedback signals.

Claim 13

An inverter system in accordance with claim 9, wherein the width of the pulses in each separate pair of pulses in the respective half cycles of the output signal phases is symmetrically varied in direct relation with the time distance between each pair of gating pulses generated by the gate pulse timer means.

Claim 14

An inverter system in accordance with claim 9, further including overcurrent detector means responsive to the current of the output signals for temporarily bypassing the error circuit means and the dwell control means whenever the current of the output signals exceeds a predetermined threshold value, the overcurrent detector means including means coupled to the gate pulse timer means of each of the gating circuit means for generating a gating pulse immediately after the occurrence of the first one of each pair of signal indications of the dwell control means when the current of the output signals exceeds the Predetermined threshold value to substantially instantaneously reduce the widths of the pairs of pulses in the half cycles of the output signal phases to a minimum value.

Claim 15

An inverter system in accordance with claim 9, further including means responsive to the current of the output signals for providing to the error circuit means a signal representing the current of the output signals, and means responsive to the voltage of the output signals for providing to the error circuit means a signal representing the voltage of the output signals, and wherein the error circuit means generates the error signal in accordance with differences between the amplitude reference signal and the larger of the two signals representing the current and voltage of the output signals.

Claim 16

An inverter system in accordance with claim 9, wherein the dwell control means includes means responsive to the first clock signal for generating a ramp signal during each cycle of the first clock signal, the ramp signal being symmetrically disposed relative to a zero reference axis, means responsive to the error signal for providing true and complementary signals equidistant from and on opposite sides of the zero reference axis, means responsive to the ramp signal and to the true signal for generating the first one of each pair of signal indications whenever the ramp signal equals the true signal, and means responsive to the ramp signal and to the complementary signal for providing the second one of each pair of signal indications whenever the ramp signal equals the complementary signal.

Claim 17

An inverter system in accordance with claim 9, wherein each gate pulse timer includes logic circuit means responsive to the second clock signal and to the pairs of signal indications from the dwell control means for providing alternate ones of the pairs of signal indications to an output thereof, second bistable means responsive to the output of the logic circuit means for assuming a first state each time a signal indication appears at the output of the logic circuit means, timing means responsive to the assumption of the first state by the second bistable means for changing the second bistable means to a second state after a selected period of time to provide a gating pulse at the output of the second bistable means in response to each signal indication at the output of the logic circuit means, the first-mentioned bistable means being coupled to the output of the second bistable means and operative to change state in response to each gating pulse at the output of the second bistable means to provide the inhibit signal.