Abstract In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.
A bias circuit comprising: at least a pair of bipolar transistors, the bases of said pair of bipolar transistors being connected to each other; a first junction field effect transistor, the source of which is connected to the emitter of one of said pair of bipolar transistors; and a second junction field effect transistor, the source of which is connected to the emitter of the other of said pair of bipolar transistors; wherein the gate electrodes of said first and second junction field effect transistors are connected to each other and to the drain electrodes of both said first and second junction field effect transistors.
Claim 2
Dependent Claim
105 words
A bias circuit comprising: at least a pair of bipolar transistors, the bases of said pair of bipolar transistors being connected to each other; a first junction field effect transistor, the source of which is connected to the emitter of one of said pair of bipolar transistors; and a second junction field effect transistor, the source of which is connected to the emitter of the other of said pair of bipolar transistors; wherein the gate electrodes of said first and second junction field effect transistors are connected to each other and to the drain electrodes of both said first and second junction field effect transistors.
Claim 3
Dependent Claim
21 words
A bias circuit as in claim 1 wherein said drain electrodes and said gate electrodes are connected to a common bus.
Claim 4
Dependent Claim
78 words
A bias circuit comprising: load means comprising a pair of bipolar transistors, each having an emitter and a base, the bases connected to each other; and a pair of junction field effect transistors, each having a source, a gate electrode, and a drain, one of the sources connected to one of the emitters, the other of the sources connected to the other of the emitters, and the gate electrodes connected to each other and connected to the drains.
Claim 5
Dependent Claim
78 words
A bias circuit comprising: load means comprising a pair of bipolar transistors, each having an emitter and a base, the bases connected to each other; and a pair of junction field effect transistors, each having a source, a gate electrode, and a drain, one of the sources connected to one of the emitters, the other of the sources connected to the other of the emitters, and the gate electrodes connected to each other and connected to the drains.