Patent US4187602A successfully refreshed from Google Patents.
US4187602A
Expired / Lapsed
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Static memory cell using field implanted resistance
Assignee: Texas Instruments Inc
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Filing: 1978-05-30
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Granted: 1980-02-12
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Expires: 1998-05-30
Abstract
Abstract A cell for a semiconductor memory of the static type employs two conventional MOS transistors along with a field implanted resistance which functions as a grounded-gate junction FET. Along with other resistor elements, these devices provide a grounded-gate amplifier with voltage gain and a source follower, creating a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:45
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; G11C11/40; G11C11/41; G11C11/412; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H10B; H10B10/00; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D84/82; H10W; H10W20/00; H10W20/01; H10W20/021; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
130 words
A method of making an integrated circuit having first and second resistors and an active circuit element comprising the steps of: forming a first resistor in the face of a silicon body by ion implanting; growing thermal oxide over said first resistor; applying a layer of polysilicon on said face at least partially overlying the thermal oxide to define a second resistor and to define an electrode of said active circuit element; implanting the polysilicon with impurity to a low level of concentration to define the resistivity of the second resistor; and introducing impurity into the polysilicon layer in all areas except that of the second resistor to form low resistance connections and said electrode; the first and second resistors and the active circuit element being interconnected in a circuit.
Claim 2
Independent Claim
130 words
A method of making an integrated circuit having first and second resistors and an active circuit element comprising the steps of: forming a first resistor in the face of a silicon body by ion implanting; growing thermal oxide over said first resistor; applying a layer of polysilicon on said face at least partially overlying the thermal oxide to define a second resistor and to define an electrode of said active circuit element; implanting the polysilicon with impurity to a low level of concentration to define the resistivity of the second resistor; and introducing impurity into the polysilicon layer in all areas except that of the second resistor to form low resistance connections and said electrode; the first and second resistors and the active circuit element being interconnected in a circuit.
Claim 3
Dependent Claim
34 words
A method according to claim 1 wherein a thin coating of thermal oxide is applied to the upper surface of the layer of polysilicon to mask the resistor and impurity is introduced by diffusion.
Claim 4
Dependent Claim
17 words
A method according to claim 1 wherein the second resistor and the gate are integrally connected together.
Claim 5
Dependent Claim
22 words
A method according to claim 2 wherein impurity is also simultaneously diffused into a region of said face of the silicon body.
Claim 6
Independent Claim
158 words
A method of making electrical connection simultaneously to a region of a face of a semiconductor body and to a strip of polycrystalline silicon on said face, comprising the steps of: exposing a contact area on said face of the body over said region, with the surrounding area on said face being covered with an insulating coating; depositing a strip of polycrystalline silicon over the insulating coating and extending into the contact area but not covering said contact area; applying another insulating coating on said face over the polycrystalline silicon and opening an aperture over the contact area to expose a portion of the region and to expose a portion of the polycrystalline silicon over the region; and applying a strip of metal to said face extending along the insulating coating and into the aperature at the contact area to engage said portion of the region and said portion of the polycrystalline silicon to provide said electrical connection.
Claim 7
Independent Claim
158 words
A method of making electrical connection simultaneously to a region of a face of a semiconductor body and to a strip of polycrystalline silicon on said face, comprising the steps of: exposing a contact area on said face of the body over said region, with the surrounding area on said face being covered with an insulating coating; depositing a strip of polycrystalline silicon over the insulating coating and extending into the contact area but not covering said contact area; applying another insulating coating on said face over the polycrystalline silicon and opening an aperture over the contact area to expose a portion of the region and to expose a portion of the polycrystalline silicon over the region; and applying a strip of metal to said face extending along the insulating coating and into the aperature at the contact area to engage said portion of the region and said portion of the polycrystalline silicon to provide said electrical connection.
Claim 8
Dependent Claim
25 words
A method according to claim 5 wherein impurity is diffused into the polycrystalline silicon and into said region of the face at the same time.
Claim 9
Dependent Claim
32 words
A method according to claim 5 wherein the step of depositing a strip of polycrystalline silicon includes at the same time forming the gate of a field effect transistor on said face.
Claim 10
Dependent Claim
27 words
A method according to claim 7 wherein the gate is integrally connected to a resistor area of the strip which is doped more lightly than the gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-11 | 1983-08-13 | 1984-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-11 | 1987-08-13 | 1988-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-11 | 1991-08-13 | 1992-02-12 | $7700.00 | Window Closed / Lapsed |