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Patent US4185209A successfully refreshed from Google Patents.
US4185209A
Expired / Lapsed
US
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CMOS boolean logic circuit
Assignee: Boeing North American Inc
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Filing: 1978-02-02
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Granted: 1980-01-22
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Expires: 1998-02-02
Abstract
Abstract Compact and high speed logic circuits that utilize CMOS technology to perform the Boolean operations A·B and A+B. The presently disclosed logic circuits are comprised of a field effect transistor and first and second logic performing diodes which are uniquely interconnected with one another so as to reduce the number of circuit components and to increase the operating speed relative to conventional logic circuits.
Inventors
- 👤 Dana C. Street
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/12
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
186 words
A logic circuit to perform functions of Boolean logic comprising: a plurality of input terminals to receive respective logic signals and an output terminal, including a first input terminal which receives a first logic signal, a second input terminal which receives a second logic signal, and a third input terminal which receives a third logic signal, said third logic signal being inverted with respect to that of said second logic signal; a first diode having respective anode and cathode terminals connected between a first of said plurality of input terminals and said output terminal, a second diode having respective anode and cathode terminals connected between a second of said plurality of input terminals and said output terminal, and a field effect transistor having a pair of conduction path terminals and a control terminal, a first conduction path terminal of said field effect transistor connected to the anode electrode of said first diode, a second conduction path terminal of said field effect transistor connected to the cathode electrode of said first diode, and said control terminal of said field effect transistor connected to said third input terminal.
Claim 2
Dependent Claim
186 words
A logic circuit to perform functions of Boolean logic comprising: a plurality of input terminals to receive respective logic signals and an output terminal, including a first input terminal which receives a first logic signal, a second input terminal which receives a second logic signal, and a third input terminal which receives a third logic signal, said third logic signal being inverted with respect to that of said second logic signal; a first diode having respective anode and cathode terminals connected between a first of said plurality of input terminals and said output terminal, a second diode having respective anode and cathode terminals connected between a second of said plurality of input terminals and said output terminal, and a field effect transistor having a pair of conduction path terminals and a control terminal, a first conduction path terminal of said field effect transistor connected to the anode electrode of said first diode, a second conduction path terminal of said field effect transistor connected to the cathode electrode of said first diode, and said control terminal of said field effect transistor connected to said third input terminal.
Claim 3
Dependent Claim
18 words
A logic circuit as defined in claim 1, wherein said field effect transistor is a p-channel MOS device.
Claim 4
Dependent Claim
18 words
A logic circuit as defined in claim 1, wherein said field effect transistor is an n-channel MOS device.
Claim 5
Dependent Claim
20 words
A logic circuit as defined in claim 1 further comprising a load capacitor connected between said output terminal and ground.
References Cited (Backward Citations)
US3356858A
Cited
US3305735A
Cited
US3683201A
Cited
US3577005A
Cited
US3676705A
Cited
US3986042A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-21 | 1983-07-23 | 1984-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-21 | 1987-07-23 | 1988-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-21 | 1991-07-23 | 1992-01-22 | $7700.00 | Window Closed / Lapsed |