Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
For use in a reproducing machine having a plurality of devices for controlling said machine, a data communications system comprising: a. a programmable master controller including: 1. master program memory storage means for storing program words defining an operating program, 2. addressing means for addressing said program words of said master program memory storage means, 3. an arithmetic and logic unit for processing said program words of said master program memory storage means, and 4. means for generating command bytes, said generating means operatively connected to said arithmetic and logic unit of said master controller, and b. a plurality of additional controllers, each of said additional controllers including: 1. means for receiving command bytes from said master controller generating means, and 2. means for providing input data bytes indicative of the operation of at least some of said devices to said master controller arithmetic and logic unit, c. said additional controllers having selected input data bits ORed together to provide at least one of said input data bytes, and d. said additional controllers simultaneously transmitting said selected input bits comprising said one input data byte to said master controller arithmetic and logic unit in response to a predetermined command byte from said master controller generating means.
Claim 2
Dependent Claim
206 words
For use in a reproducing machine having a plurality of devices for controlling said machine, a data communications system comprising: a. a programmable master controller including: 1. master program memory storage means for storing program words defining an operating program, 2. addressing means for addressing said program words of said master program memory storage means, 3. an arithmetic and logic unit for processing said program words of said master program memory storage means, and 4. means for generating command bytes, said generating means operatively connected to said arithmetic and logic unit of said master controller, and b. a plurality of additional controllers, each of said additional controllers including: 1. means for receiving command bytes from said master controller generating means, and 2. means for providing input data bytes indicative of the operation of at least some of said devices to said master controller arithmetic and logic unit, c. said additional controllers having selected input data bits ORed together to provide at least one of said input data bytes, and d. said additional controllers simultaneously transmitting said selected input bits comprising said one input data byte to said master controller arithmetic and logic unit in response to a predetermined command byte from said master controller generating means.
Claim 3
Dependent Claim
60 words
A data communications system as recited in claim 1, wherein said master controller further includes output data byte generating means, said output data byte generating means operatively connected to said arithmetic and logic unit of said master controller, and means for transmitting output data bytes from said output data byte generating means to said additional controllers for controlling said machine.
Claim 4
Dependent Claim
48 words
A data communications system as recited in claim 1 wherein said master controller further includes means for generating identifying addresses for said additional controllers and means for transmitting said identifying addresses to said additional controllers, each of said additional controllers including decode logic means for decoding said addresses.
Claim 5
Dependent Claim
21 words
A data communications system as recited in claim 1 wherein at least one of said additional controllers is a programmable controller.
Claim 6
Dependent Claim
28 words
A data communications system as recited in claim 1 wherein said simultaneously transmitted data bytes provide an address for addressing a predetermined subroutine in said memory storage means.
Claim 7
Dependent Claim
33 words
A data communications system as recited in claim 1 including means for transmitting said input data bytes from said additional controllers in bit serial form to said master controller arithmetic and logic unit.