Patent US4182962A successfully refreshed from Google Patents.
US4182962A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor temperature compensation circuit
Assignee: Toshiba Corp
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Filing: 1977-10-12
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Granted: 1980-01-08
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Expires: 1997-10-12
Abstract
Abstract A semiconductor device which comprises a first current path formed of a first load, an n number of first transistors, each of whose bases is supplied with an input signal, a second transistor whose base is connected to a first bias power source, and an emitter resistor of said second transistor all connected in series between power supply terminals; and a second current path formed of a second load, a third transistor whose base is connected to a second bias power source through a base resistor, and an emitter resistor of the third transistor all connected in series between the power supply terminals, and wherein the resistance of the base resistor is chosen to be n times as large as that of the emitter resistor of the third transistor, thereby equalizing the amounts of current running through the first and second current paths.
Inventors
- 👤 Shinichiro Taguchi
- 👤 Tokio Aketagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:45
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/22; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G05F3/222; G05F3/225
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
172 words
A compensating circuit comprising: a first signal path including: a first transistor having a base, a collector and an emitter, said emitter coupled to a first potential source, and said base coupled to a second potential source, said transistor establishing a first constant current through said collecter; n transistors cascade-coupled to said collector of said first transistor, said first constant current flowing through said cascade of transistors; and a first load coupled between said cascade of n transistors and a third potential source; a second signal path including; a second transistor having a base, a collector and an emitter, said emitter coupled to said first potential source through an emitter impedance and said base coupled to a fourth potential source through a base impedance, said transistor establishing a second constant current; and a second load coupled between said collector of said second transistor and said third potential source, said second constant current flowing therethrough, wherein the ratio between said base and emitter impedances of said second transistor is substantially equal to n.
Claim 2
Dependent Claim
172 words
A compensating circuit comprising: a first signal path including: a first transistor having a base, a collector and an emitter, said emitter coupled to a first potential source, and said base coupled to a second potential source, said transistor establishing a first constant current through said collecter; n transistors cascade-coupled to said collector of said first transistor, said first constant current flowing through said cascade of transistors; and a first load coupled between said cascade of n transistors and a third potential source; a second signal path including; a second transistor having a base, a collector and an emitter, said emitter coupled to said first potential source through an emitter impedance and said base coupled to a fourth potential source through a base impedance, said transistor establishing a second constant current; and a second load coupled between said collector of said second transistor and said third potential source, said second constant current flowing therethrough, wherein the ratio between said base and emitter impedances of said second transistor is substantially equal to n.
Claim 3
Dependent Claim
26 words
A compensating circuit according to claim 1, wherein said emitter and base impedances of said second transistor are resistors, their resistance satisfy the following relationship: ##EQU15##
Claim 4
Dependent Claim
49 words
A compensating circuit according to claim 1, wherein said emitter of said first transistor is coupled to said first potential source through an emitter impedance conducting said first constant current, said emitter impedance having a value selected such that said first and second constant currents have a predetermined ratio.
Claim 5
Dependent Claim
25 words
A compensating circuit according to claim 3, wherein each of said n cascaded transistors of said first signal path is part of a differential amplifier.
Claim 6
Dependent Claim
284 words
A compensating circuit comprising: a first signal path including: a first transistor having a base, an emitter, and a collector, said emitter coupled through a first emitter impedance to a first potential source, said base of said first transistor coupled to a bias source, said transistor establishing a first constant current; a first differential amplifier having emitters commonly coupled to said collector of said first transistor and having first and second collectors, said differential amplifier having bases coupled to a first common signal source; a double balanced differential amplifier including second and third differential amplifiers, said second differential amplifier having emitters commonly coupled to said first collector of said first differential amplifier and said third differential amplifier having emitters commonly coupled to said second collector of said first differential amplifier, said second and third differential amplifiers adapted to receive second and third input signals, each of said second and third differential amplifiers having first and second collectors; said second collectors coupled to a second potential source; and a first load coupling said second potential source to said first collectors of said second and third differential amplifiers; and a second signal path including; a second transistor having a base, an emitter and a collector, said emitter coupled through a second emitter impedance to said first potential source, and said base coupled through a base impedance to said bias source, said second transistor establishing a second constant current; and a second load coupling said collector of said second transistor to said second potential source, wherein the ratio of said base impedance to said second emitter impedance is substantially equal to n and wherein said second emitter impedance is essentially double that of said first emitter impedance.
Claim 7
Dependent Claim
284 words
A compensating circuit comprising: a first signal path including: a first transistor having a base, an emitter, and a collector, said emitter coupled through a first emitter impedance to a first potential source, said base of said first transistor coupled to a bias source, said transistor establishing a first constant current; a first differential amplifier having emitters commonly coupled to said collector of said first transistor and having first and second collectors, said differential amplifier having bases coupled to a first common signal source; a double balanced differential amplifier including second and third differential amplifiers, said second differential amplifier having emitters commonly coupled to said first collector of said first differential amplifier and said third differential amplifier having emitters commonly coupled to said second collector of said first differential amplifier, said second and third differential amplifiers adapted to receive second and third input signals, each of said second and third differential amplifiers having first and second collectors; said second collectors coupled to a second potential source; and a first load coupling said second potential source to said first collectors of said second and third differential amplifiers; and a second signal path including; a second transistor having a base, an emitter and a collector, said emitter coupled through a second emitter impedance to said first potential source, and said base coupled through a base impedance to said bias source, said second transistor establishing a second constant current; and a second load coupling said collector of said second transistor to said second potential source, wherein the ratio of said base impedance to said second emitter impedance is substantially equal to n and wherein said second emitter impedance is essentially double that of said first emitter impedance.
References Cited (Backward Citations)
US3781648A
Cited
US3970947A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-07 | 1983-07-09 | 1984-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-07 | 1987-07-09 | 1988-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-07 | 1991-07-09 | 1992-01-08 | $7700.00 | Window Closed / Lapsed |