Patent US4180827A successfully refreshed from Google Patents.
US4180827A
Expired / Lapsed
US
⏱️ 0.0 years remaining
NPN/PNP Fabrication process with improved alignment
Assignee: International Business Machines Corp
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Filing: 1977-08-31
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Granted: 1979-12-25
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Expires: 1997-08-31
Abstract
Abstract A double diffused, lateral PNP structure is disclosed which may be formed simultaneously with a vertical NPN structure. The novel feature of the structure is believed to be the vertical projection of the N-type base region for the PNP, down through the surrounding diffused P-type collector and into an N-type epitaxial layer between the collector diffusion and a buried sub-base, an N-type sub-base to electrically contact the base. The N-type epitaxial layer serves as the extrinsic base region permitting contact with the surface. The double diffused base and emitter structure permits a precise intrinsic base width to be formed for the lateral PNP. Thus, a high performance PNP can be constructed with compatible high performance NPNs on the same substrate.
Inventors
- 👤 Harlan R. Gates
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D10/00; H10D10/60; H10D84/63
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
145 words
A lateral PNP bipolar transistor structure, comprising: an epitaxial layer of a first conductivity type over a buried sub-base region of said first conductivity type; a collector region of a second conductivity type formed in the surface of said epitaxial layer over said buried sub-base region; a base region of said first conductivity type formed over said collector region through a mask window and projecting through said collector region into said epitaxial layer and electrically contacting said sub-base region; an emitter region of said second conductivity type formed within said base region through said mask window, defining an intrinsic lateral base region between the lateral sides of the emitter region and the base region; a base contact on the surface of said epitaxial layer for making electrical contact with said base region; whereby a lateral PNP is formed with a reduced collector to base capacitance.
Claim 2
Dependent Claim
145 words
A lateral PNP bipolar transistor structure, comprising: an epitaxial layer of a first conductivity type over a buried sub-base region of said first conductivity type; a collector region of a second conductivity type formed in the surface of said epitaxial layer over said buried sub-base region; a base region of said first conductivity type formed over said collector region through a mask window and projecting through said collector region into said epitaxial layer and electrically contacting said sub-base region; an emitter region of said second conductivity type formed within said base region through said mask window, defining an intrinsic lateral base region between the lateral sides of the emitter region and the base region; a base contact on the surface of said epitaxial layer for making electrical contact with said base region; whereby a lateral PNP is formed with a reduced collector to base capacitance.
Claim 3
Dependent Claim
327 words
A lateral PNP transistor formed in an integrated circuit including vertical NPN transistors, comprising: an epitaxial layer of a first (N) conductivity type, having a plurality of buried high conductivity regions of said first conductivity type therein, divided into a first plurality of isolated regions containing PNP transistors and a second plurality of isolated regions containing NPN transistors; a plurality of regions of a second conductivity type (P) in the surface of said substrate, with a first one in one of said first plurality isolated regions serving as the collector region for said lateral PNP and a second one in one of said second plurality of isolated regions serving as the base region for said vertical NPN transistor, with each one of said plurality of regions of said second conductivity type lying over a corresponding one of said buried, high conductivity regions; a region of said first conductivity type (N) formed through a window over said collector of said lateral PNP and projecting through said collector into said epitaxial layer and electrically contacting said buried high conductivity region as the base of said lateral PNP; a region of said second conductivity (P) type formed in said substrate through said window over said collector of said lateral PNP and contained within said base region for said lateral PNP, as the emitter of said lateral PNP; a plurality of regions of said first conductivity type, a first one of which is formed in said epitaxial layer in said one of said first plurality of isolated regions, serving as the base contact for said PNP transistor, a second one of which is formed in said epitaxial layer in said one of said second plurality of isolated regions as the collector contact for said NPN transistor and a third one of which is formed in said base region of said NPN transistor as the emitter thereof; whereby compatible, high performance PNP and NPN transistors can be formed in an integrated circuit.
Claim 4
Dependent Claim
327 words
A lateral PNP transistor formed in an integrated circuit including vertical NPN transistors, comprising: an epitaxial layer of a first (N) conductivity type, having a plurality of buried high conductivity regions of said first conductivity type therein, divided into a first plurality of isolated regions containing PNP transistors and a second plurality of isolated regions containing NPN transistors; a plurality of regions of a second conductivity type (P) in the surface of said substrate, with a first one in one of said first plurality isolated regions serving as the collector region for said lateral PNP and a second one in one of said second plurality of isolated regions serving as the base region for said vertical NPN transistor, with each one of said plurality of regions of said second conductivity type lying over a corresponding one of said buried, high conductivity regions; a region of said first conductivity type (N) formed through a window over said collector of said lateral PNP and projecting through said collector into said epitaxial layer and electrically contacting said buried high conductivity region as the base of said lateral PNP; a region of said second conductivity (P) type formed in said substrate through said window over said collector of said lateral PNP and contained within said base region for said lateral PNP, as the emitter of said lateral PNP; a plurality of regions of said first conductivity type, a first one of which is formed in said epitaxial layer in said one of said first plurality of isolated regions, serving as the base contact for said PNP transistor, a second one of which is formed in said epitaxial layer in said one of said second plurality of isolated regions as the collector contact for said NPN transistor and a third one of which is formed in said base region of said NPN transistor as the emitter thereof; whereby compatible, high performance PNP and NPN transistors can be formed in an integrated circuit.
References Cited (Backward Citations)
US4054900A
Cited
US4058419A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-24 | 1983-06-25 | 1983-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-24 | 1987-06-25 | 1987-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-24 | 1991-06-25 | 1991-12-25 | $7700.00 | Window Closed / Lapsed |