US4058419A
Expired / Lapsed
US
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Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
Assignee: Toshiba Corp
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Filing: 1975-12-24
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Granted: 1977-11-15
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Expires: 1995-12-24
Abstract
Abstract A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.
Inventors
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
- 👤 Satoshi Shinozaki
- 👤 Junichi Nakamura
- 👤 Shintaro Ito
- 👤 Yoshio Nishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/65; H10P; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
225 words
A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of forming said semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type; forming an insulation film on said selected portion of the semiconductor layer; forming a first opening through said insulation film; doping an impurity of one conductivity type into said selected portion of the semiconductor layer through said first opening thereby forming a first region of said one conductivity type which reaches said semiconductor substrate; forming a second opening through said insulation film doping an impurity of the opposite conductivity type into said first region of the one conductivity type and said semiconductor layer of the opposite conductivity type respectively through said first and second openings in an oxidizing atmosphere thereby forming a first region of the opposite conductivity type completely within said first region of said one conductivity type and a second region of the opposite conductivity type in said selected portion of the layer; semiconductor forming a third opening through said insulation film doping an impurity of one conductivity type into said selected portion of the semiconductor layer through said third opening in an oxidizing atmosphere thereby forming a second region of said one conductivity type in said semiconductor layer of the opposite conductivity type.
Claim 2
Independent Claim
225 words
A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of forming said semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type; forming an insulation film on said selected portion of the semiconductor layer; forming a first opening through said insulation film; doping an impurity of one conductivity type into said selected portion of the semiconductor layer through said first opening thereby forming a first region of said one conductivity type which reaches said semiconductor substrate; forming a second opening through said insulation film doping an impurity of the opposite conductivity type into said first region of the one conductivity type and said semiconductor layer of the opposite conductivity type respectively through said first and second openings in an oxidizing atmosphere thereby forming a first region of the opposite conductivity type completely within said first region of said one conductivity type and a second region of the opposite conductivity type in said selected portion of the layer; semiconductor forming a third opening through said insulation film doping an impurity of one conductivity type into said selected portion of the semiconductor layer through said third opening in an oxidizing atmosphere thereby forming a second region of said one conductivity type in said semiconductor layer of the opposite conductivity type.
Claim 3
Dependent Claim
56 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 1, including the additional step of reopening said first, second and third openings and forming electrode films on said first and second regions of the opposite conductivity type and on said second region of the one conductivity type region through the respective openings.
Claim 4
Dependent Claim
53 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 1, wherein the step of forming said openings includes forming said first opening like a grid, thereby dividing said insulation film into a plurality of sections, and forming said second and third openings within each section of said insulation film.
Claim 5
Dependent Claim
41 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 1, wherein said first opening is formed in an annular configuration, and said second and third openings are formed within the area circumscribed by said first annular opening.
Claim 6
Dependent Claim
107 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 1, wherein said step of doping an impurity of one conductivity type includes the steps of forming an oxide layer having an impurity of said one conductivity type over said selected portion of the insulation film and said first opening, doping the impurity of said one conductivity type contained in said oxide layer into said selected portion of the semiconductor layer through said first opening in a non-oxidizing atmosphere, thereby forming a first region of said one conductivity type which reaches said semiconductor substrate; and removing said oxide layer thereby reopening said first opening.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |