Patent US4177457A successfully refreshed from Google Patents.
US4177457A
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US
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Floating point playback system
Assignee: Texaco Inc
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Filing: 1977-12-12
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Granted: 1979-12-04
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Expires: 1997-12-12
Abstract
Abstract A system for playing back a wide dynamic amplitude range analog signal that is digitized in floating point word form. The word being represented in digital signal form by the general algebraic form Q=±AB -N where Q represents the amplitude of the analog signal, A represents the mantissa, B indicates the radix of the number system used, N represents the number of fixed gain amplifier steps, and is the exponent of B, each word is represented by a first plurality of binary bits representing N. The playback system includes a first converter receiving a reference voltage which converts the bits representing A to an interim analog signal. A second converter converts the bits representing N to a plurality of control signals. A resistor network is connected to ground and has N number of inputs and an output. The resistor network provides a signal which is a reduction of the interim analog signal applied to one of the inputs, the reduction being determined by which input the interim analog signal was applied to. Each switch of a plurality of switches is connected to the first and second converters, to ground and to a corresponding input of the resistor network. Each switch is responsive to the corresponding control signal either to apply the interim analog signal to the corresponding input of the resistor network when the control signal is at another logic level. An amplifier connected to the resistor network amplifies the output signal from the resistor network to provide an amplified signal corresponding to the wide dynamic amplitude range analog signal.
Inventors
- 👤 Donald L. Howlett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:54
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/662
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
432 words
In a system wherein a wide dynamic amplitude range analog signal is digitized in floating point word form, said word being represented in digital signal form by the general algebraic form Q= ± AB -N wherein Q represents the amplitude of the analog signal, A represents the mantissa, B indicates the radix of the number system used, N is the exponent, and wherein said word is represented by a first plurality of binary bits representing ±A and a second plurality of binary bits representing N, a system for recreating an analog signal from the floating point words comprising: first means for converting said bits representing A to an interim analog signal; second means for converting said bits representing N to a plurality of control signals; resistor network means for providing a signal which is a reduction of a signal applied to the resistor network means, said resistor network means including a first plurality of N number of resistor, having a first resistor and an Nth resistor, and all resistors in the first plurality of resistors have the same resistance value; a second plurality of N number of serially connected resistors having a first resistor and an Nth resistor, all resistors of the second plurality of resistors have the same resistance value, and connected so that each connection of two resistors of the second plurality of resistors is connected to one end of a corresponding resistor in the first plurality of resistors, and a first resistor connecting the Nth resistor of the second plurality of resistors to ground, where the first resistor has a resistance value that is one-seventh of the value of the resistance value of a resistor in the second plurality of resistors and a resistance value that is seven-eighths of the resistance value of a resistor in the first plurality of resistors; a plurality of switching means, each switching means being connected to the first and second converting means, to ground and to the unconnected end of a corresponding resistor of the first plurality of resistors for applying the interim analog signal to the corresponding resistor of the first plurality of resistors when a corresponding control signal is at one logic level and for connecting the corresponding resistor of the first plurality of resistor network means to ground when the corresponding control signal is at another logic level; and amplifier means connected to the unconnected end of the first resistor of the second plurality of resistors for amplifying the signal provided by the resistor network means to provide an amplified signal corresponding to the wide dynamic amplitude range analog signal.
Claim 2
Dependent Claim
432 words
In a system wherein a wide dynamic amplitude range analog signal is digitized in floating point word form, said word being represented in digital signal form by the general algebraic form Q= ± AB -N wherein Q represents the amplitude of the analog signal, A represents the mantissa, B indicates the radix of the number system used, N is the exponent, and wherein said word is represented by a first plurality of binary bits representing ±A and a second plurality of binary bits representing N, a system for recreating an analog signal from the floating point words comprising: first means for converting said bits representing A to an interim analog signal; second means for converting said bits representing N to a plurality of control signals; resistor network means for providing a signal which is a reduction of a signal applied to the resistor network means, said resistor network means including a first plurality of N number of resistor, having a first resistor and an Nth resistor, and all resistors in the first plurality of resistors have the same resistance value; a second plurality of N number of serially connected resistors having a first resistor and an Nth resistor, all resistors of the second plurality of resistors have the same resistance value, and connected so that each connection of two resistors of the second plurality of resistors is connected to one end of a corresponding resistor in the first plurality of resistors, and a first resistor connecting the Nth resistor of the second plurality of resistors to ground, where the first resistor has a resistance value that is one-seventh of the value of the resistance value of a resistor in the second plurality of resistors and a resistance value that is seven-eighths of the resistance value of a resistor in the first plurality of resistors; a plurality of switching means, each switching means being connected to the first and second converting means, to ground and to the unconnected end of a corresponding resistor of the first plurality of resistors for applying the interim analog signal to the corresponding resistor of the first plurality of resistors when a corresponding control signal is at one logic level and for connecting the corresponding resistor of the first plurality of resistor network means to ground when the corresponding control signal is at another logic level; and amplifier means connected to the unconnected end of the first resistor of the second plurality of resistors for amplifying the signal provided by the resistor network means to provide an amplified signal corresponding to the wide dynamic amplitude range analog signal.
Claim 3
Dependent Claim
81 words
A system as described in claim 1 which the amplifier means includes an amplifier having as inverting input connected to the first resistors of the first and second pluralities of resistors, a non-inverting input and an output; a feedback network including a feedback resistor connecting the inverting input of the amplifier to the output of the amplifier, and a feedback capacitor connected in parallel with the feedback resistor; and a second resistor connecting the non-inverting input of the amplifier to ground.
Claim 4
Dependent Claim
65 words
A system as described in claim 2 in which the first converter means includes means for providing a sawtooth reference voltage, and a digital-to-analog converter receiving the bits corresponding to the mantissa A and the sawtooth reference voltage and having an output connected to all the switching means and which converts the bits to the interim analog signal in accordance with the sawtooth reference voltage.
Claim 5
Dependent Claim
121 words
A system as described in claim 3 in which the second converter means includes pulse means connected to the reference voltage means for providing a pulse each time a peak of the sawtooth reference voltage occurs, K signal means connected to the pulse means for counting the pulses and providing K digital signals in accordance with the count, subtracting means connected to the K signal means and receiving the digital bits corresponding to (N) for subtracting the digital bits from the K signals to provide digital signals corresponding to K-(N) and decoding means connected to subtracting means and to all the switching means for decoding the digital signals from the subtracting means to provide the control signals to the switching means.
Claim 6
Dependent Claim
28 words
A system as described in claim 4 in which the resistance values of the resistors are selected in accordance with the radix B of the number system used.
Claim 7
Dependent Claim
35 words
A system as described in claim 5 in which the ratio of the resistance of the feedback resistor to the resistance value of a resistor in the first plurality of resistors determines a scaling factor.
Claim 8
Dependent Claim
51 words
A system as described in claim 6 in which the resistance value of the second resistor is equal to the ratio of the product of the resistance values of the first resistor and the feedback resistor to the sum of the resistance values of the first resistor and the feedback resistor.
Claim 9
Dependent Claim
23 words
A system as described in claim 1 further comprising recording means connected to the output of the amplifier for recording the amplified signal.
Claim 10
Dependent Claim
55 words
A system as described in claim 8 in which a plurality of wide dynamic amplitude range analog signals are represented by multiplexed floating point digital words; and further comprising means for demultiplexing the amplified signal to a plurality of analog signals corresponding on one for one basis to the wide dynamic amplitude range analog signals.
Claim 11
Dependent Claim
30 words
A system as described in claim 9 in further comprising filter means connecting the output of the demultiplexer to the recording means for smoothing the amplified signal prior to recording.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-03 | 1983-06-04 | 1983-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-03 | 1987-06-04 | 1987-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-03 | 1991-06-04 | 1991-12-04 | $7700.00 | Window Closed / Lapsed |