US3579232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-linear digital to analog decoder with a smooth characteristic
Assignee: International Standard Electric Corp
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Filing: 1969-04-23
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Granted: 1971-05-18
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Expires: 1989-04-23
Abstract
Abstract A digital to analog decoder or converter is disclosed. The decoder has a smooth nonlinear characteristic of the hyperbolic sine type. This smooth characteristic is contrasted to a nonlinear characteristic approximated by a plurality of straight line segments in the prior art. The decoder of this case includes a register to store a 7-digit code to be decoded. A first decoder circuit decodes the last four digits of the 7-digit code. Two groups of current generators (a first selection circuit) responding to the output of the first decoder produce two currents. A bipolar inverter (a second selection circuit) responding to the first of the last four digits directs the two currents to a third selection circuit. The third selection circuit responds to the output of of a second decoder to direct the two currents to the appropriate one of two ladder attenuators, the outputs of which produce the analog signal. The second decoder responds to the first three digits of the 7-digit code.
Inventors
- 👤 Pierre Girard
- 👤 Claude Paul Henri Lerouge
- 👤 Marc Andre Regnier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:05
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
A nonlinear digital-to-analog decoder adapted to decode numbers in a natural binary code with n n1+n2 digits, and having a smooth logarithmic characteristic y f(x) given by the equation wherein m represents the curvature of said characteristic, said decoder comprising a register for receiving and storing digital signals to be decoded, a first decoder circuit for selecting a primary control signal in response to a first group (n2) of said digital signals, means responsive to said selected primary control signal for providing currents determined by said first group of digital signals, means for deriving a secondary control signal, means responsive to said secondary control signal to transmit said currents to a tertiary selection circuit, a second decoder circuit responsive to a second group (n1) of said digital signals to select a tertiary control signal for controlling said tertiary selection circuits, and ladder attenuators responsive to signals from said tertiary selection circuit to provide analog output signals proportional to the received digital signals.
Claim 2
Dependent Claim
162 words
A nonlinear digital-to-analog decoder adapted to decode numbers in a natural binary code with n n1+n2 digits, and having a smooth logarithmic characteristic y f(x) given by the equation wherein m represents the curvature of said characteristic, said decoder comprising a register for receiving and storing digital signals to be decoded, a first decoder circuit for selecting a primary control signal in response to a first group (n2) of said digital signals, means responsive to said selected primary control signal for providing currents determined by said first group of digital signals, means for deriving a secondary control signal, means responsive to said secondary control signal to transmit said currents to a tertiary selection circuit, a second decoder circuit responsive to a second group (n1) of said digital signals to select a tertiary control signal for controlling said tertiary selection circuits, and ladder attenuators responsive to signals from said tertiary selection circuit to provide analog output signals proportional to the received digital signals.
Claim 3
Dependent Claim
45 words
A nonlinear digital to analog decoder as claimed in claim 1, in which the means responsive to said primary control signal includes two current generators for providing currents which increase in magnitude in accordance with the value represented by the first group of digital signals.
Claim 4
Dependent Claim
32 words
A nonlinear digital-to-analog decoder as claimed in claim 2, in which a bipolar inverter controls the switching of the currents supplied by the two generators in response to the secondary control signal.
Claim 5
Dependent Claim
31 words
A nonlinear digital-to-analog decoder as claimed in claim 3, in which the tertiary selection circuit includes switching means for switching the currents received from the bipolar inverter to the ladder attenuators.
Claim 6
Dependent Claim
62 words
A nonlinear digital-to-analog decoder as claimed in claim 1, in which the ladder attenuators are formed by two sets of cells totaling 2n1 cells bringing an attenuation of d2 m (n1 1) per cell, one of said sets of cells providing a voltage and the other set of cells providing a voltage whereby the difference is equal to the decoded voltage x.
Claim 7
Dependent Claim
76 words
A nonlinear digital to analog decoder as claimed in claim 1, in which the register stores a 7-digit code (n 7), the first decoder circuit responds to the last four (n2 4) of said digits to derive the primary control signal, the secondary control signal is derived from the first of the last four digits, and the second decoder circuit responds to the first three (n1 3) of said digits to derive the tertiary control signal.
References Cited (Backward Citations)
US3296611A
Cited
US3298017A
Cited
US3310799A
Cited
US3305857A
Cited
US3396380A
Cited
US3366947A
Cited
US3377586A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |