Device for detecting errors in a digital transmission system

Claim 2

Apparatus for detecting errors in a digital transmission system of a type wherein the signal transmitted has a bounded digital running total which can assume any one of n distinct states, characterized by: a synchronous up/down counter having an up-count input and a down-count input both of which are connected to receive said transmitted signal, said counter including K bi-stable multivibrators each of which has at least one input and first and second, complementary, outputs, each multivibrator having a logic arrangement associated with the at least one input thereto, said logic arrangement having a plurality of inputs connected to said up-count input, to said down-count input, and to selected ones of the first and second outputs of the remaining (K-1) multi-vibrators in the up/down counter; and an end-decoder sensitive to any overflow of a lowest or highest count in said up/down counter, said decoder including first and second logic circuits having inputs respectively connected to (a) said up-count input and the first outputs of said K bi-stable multivibrators, and (b) said down-count input and the second outputs of said K bi-stable multivibrators, and wherein: K, the number of bistable multi-vibrators in said up/down counter, is an integer which satisfies the inequality: 2.sup.K-1 <n≦2.sup.K.

Claim 3

The apparatus according to claim 1 wherein each of the bi-stable multivibrators in said up/down counter comprises a J-K type flip-flop having a J input, a K input and first and second, complementary, Q, Q outputs.

Claim 4

The apparatus according to claim 2 wherein said transmitted signal is a ternary signal with n=8, i.e., said signal can assume any of 8 distinct states, said apparatus being further characterized in that: said up-count input, hereinafter designated T + , receives the positive and zero values of said ternary signal; said down-count input, hereinafter designated T - , receives the negative and zero values of said ternary signal, these negative and zero signals having previously undergone a polarity inversion; and K=3, i.e., said up/down counter comprises 3 J-K type flip-flops, the logic arrangements associated with each of said flip-flops being interconnected such that their inputs and outputs satisfy the following logic equations: for the first flip-flop: J.sub.1 =T.sup.+ ·T.sup.- +T.sup.- ·Q.sub.2 ·Q.sub.3 K.sub.1 =T.sup.+ ·T.sup.- +T.sup.+ ·Q.sub.2 ·Q.sub.3 for the second flip-flop: J.sub.2 =T.sup.+ ·Q.sub.1 +T.sup.- ·Q.sub.1 +T.sup.+ ·Q.sub.3 K.sub.2 =T.sup.+ ·Q.sub.1 +T.sup.- ·Q.sub.1 +T.sup.- ·Q.sub.3 for the third flip-flop: J.sub.3 =T.sup.+ +Q.sub.1 +Q.sub.2 K.sub.3 =T.sup.- +Q.sub.1 +Q.sub.2 said end decoder performing the logic function: T.sup.+ ·Q.sub.1 ·Q.sub.2 ·Q.sub.3 +T.sup.- ·Q.sub.1 ·Q.sub.2 ·Q.sub.3, the magnitudes J, K and Q designating respectively the logic levels of the J input, the K input and the Q output of said J-K type flip-flops and the subscripts 1, 2 or 3 indicating that the magnitude refers to the first, second or third flip-flop, respectively.

Claim 5

The apparatus according to claim 3 wherein each of said logic arrangements comprises a plurality of OR-gates and the first and second logic circuits in said end-decoder each comprises an OR-gate.

Claim 6

The apparatus according to claim 4 wherein each of said OR-gates is a negative logic OR-gate, i.e., a NOR-gate.

Claim 7

The apparatus according to claim 2 wherein said transmitted signal is a ternary signal with n=6, i.e., said signal can assume any of 6 distinct states, said apparatus being further characterized in that: said up-count input, hereinafter designated T + , receives the positive and zero values of said ternary signal; said down-count input, hereinafter designated T - , receives the negative and zero values of said ternary signal, these negative and zero signals having previously undergone a polarity inversion; K=3, i.e., said up/down counter comprises three J-K type arrangements associated with each of said flip-flops being interconnected such that their inputs and outputs satisfy the following logic equations: for the first flip-flop: J.sub.1 =T.sup.+ +T.sup.- +T.sup.- +Q.sub.2 +Q.sub.3 K.sub.1 =T.sup.+ +T.sup.- +T.sup.+ +Q.sub.3 for the second flip-flop: J.sub.2 =T.sup.- +Q.sub.1 +T.sup.+ +Q.sub.3 +Q.sub.1 +Q.sub.3 K.sub.2 =T.sup.- +Q.sub.1 +T.sup.+ +Q.sub.1 for the third flip-flop: J.sub.3 =T.sup.+ +Q.sub.1 +Q.sub.2 K.sub.3 =T.sup.- +Q.sub.1 +Q.sub.2 said end decoder performing the logic function: T.sup.+ ·Q.sub.1 ·Q.sub.2 ·Q.sub.3 +T.sup.- ·Q.sub.1 ·Q.sub.2 ·Q.sub.3, the magnitudes J, K and Q designating respectively the logic levels of the J input, the K input and the Q output of said J-K type flip-flops and the subscripts 1, 2 or 3 indicating that the magnitude refers to the first, second or third flip-flop, respectively.

Claim 8

The apparatus according to claim 6 wherein each of said logic arrangements comprises a plurality of OR-gates and said first and second logic circuits in said end-decoder each comprises an OR-gate.

Claim 9

The apparatus according to claim 7 wherein each of said OR-gates comprises a negative logic OR-gate, i.e., a NOR-gate.

Claim 10

The apparatus according to claim 1 wherein each of the bi-stable multivibrators in said up/down counter comprises a D-type flip-flop having the a D input and first and second, complementary, Q, Q outputs.

Claim 11

The apparatus according to claim 9 wherein said transmitted signal is a ternary signal with n=8, i.e., said signal can assume any of 8 distinct states, said apparatus being further characterized in that: said up-count input, hereinafter designated T + , receives the positive and zero values of said ternary signal; said down-count input, hereinafter designated T - , receives the negative or zero values of said ternary signal, these negative and zero signals having previously undergone a polarity inversion, and K=3, i.e., said up/down counter comprises 3 D-type flip-flops, the logic arrangements associated with each of said flip-flops being interconnected such that their inputs and outputs satisfy the following logic equations: for the first flip-flop: D.sub.1 =T.sup.+ +T.sup.- +Q.sub.1 +T.sup.- +Q.sub.2 +Q.sub.3 +T.sup.- +Q.sub.2 +Q.sub.3 +T.sup.+ +Q.sub.2 +Q.sub.3 +T.sup.+ +Q.sub.2 +Q.sub.3 for the second flip-flop: D.sub.2 =T.sup.+ +T.sup.- +Q.sub.2 +T.sup.- +Q.sub.1 +Q.sub.3 +T.sup.+ +Q.sub.1 +Q.sub.3 +Q.sub.1 +Q.sub.2 for the third flip-flop: D.sub.3 =T.sup.- +Q.sub.3 +T.sup.+ Q.sub.1 +Q.sub.2 +Q.sub.1 +Q.sub.3 +Q.sub.2 +Q.sub.3 said end decoder performing the logic function: T.sup.+ ·Q.sub.1 ·Q.sub.2 ·Q.sub.3 +T.sup.- ·Q.sub.1 ·Q.sub.2 ·Q.sub.3, the magnitudes D and Q designating respectively the logic levels at the D input and at the Q output of said D-type flip-flops and the subscripts 1, 2 and 3 indicating that the magnitude refers to the first, second and third flip-flop, respectively.

Claim 12

The apparatus according to claim 10 wherein each of said logic arrangements comprises a plurality of OR-gates and the first and second logic circuits in said end-decoder each comprises an OR-gate.

Claim 13

The apparatus according to claim 11 wherein each of said OR-gates is a negative logic OR-gate, i.e., a NOR-gate.

Claim 14

The apparatus according to claim 9 wherein said transmitted signal is a ternary signal with n=6, i.e., said signal can assume any of 6 distinct states, said apparatus being further characterized in that: said up-count input, hereinafter designated T + , receives the positive and zero values of said ternary signal; said down-count input, hereinafter designated T - , receives the negative and zero values of said ternary signal, these negative and zero signals having previously undergone a polarity inversion; K=3, i.e., said up/down counter comprises three D-type flip-flops, the logic arrangements associated with each of said flip-flops being interconnected such that their inputs and outputs satisfy the following logic equations: for the first flip-flop: D.sub.1 =T.sup.+ +T.sup.- Q.sub.1 +T.sup.- +Q.sub.2 +Q.sub.3 +T.sup.+ +Q.sub.3 +T.sup.+ +Q.sub.2 for the second flip-flop: D.sub.2 =T.sup.- +Q.sub.2 +T.sup.+ +Q.sub.1 +Q.sub.1 +Q.sub.2 +Q.sub.3 for the third flip-flop: D.sub.3 =T.sup.- +Q.sub.3 +T.sup.+ +Q.sub.1 +Q.sub.2 +Q.sub.1 +Q.sub.2 said end decoder performing the logic function: T.sup.+ ·Q.sub.1 ·Q.sub.2 ·Q.sub.3 +T.sup.- ·Q.sub.1 ·Q.sub.2 ·Q.sub.3, the magnitudes D and Q designating respectively the logic levels at the D input and at the Q output of said D-type flip-flops and the subscripts 1, 2 and 3 indicating that the magnitude refers to the first, second and third flip-flops, respectively.

Claim 15

The apparatus according to claim 13 wherein each of said logic arrangements comprises a plurality of OR-gates and the first and second logic circuits in said end-decoder each comprises and OR-gate.

Claim 16

The apparatus according to claim 14 wherein each of said OR-gates comprises a negative logic OR-gate, i.e., a NOR-gate.