US3842401A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ternary code error detector for a time-division multiplex, pulse-code modulation system
Assignee: General Electric Co
•
Filing: 1973-09-10
•
Granted: 1974-10-15
•
Expires: 1993-09-10
Abstract
Abstract In a time-division multiplex, pulse-code modulation system, each sequence of four binary pulses representing information is converted to a group of three ternary pulses for transmission to a receiver. The conversions are made either in a positive mode if the prior net polarity is negative or in a negative mode if the prior net polarity is zero or positive. Use of the positive and negative modes insures that the net positive and the net negative polarities are kept within selected limits. At the receiver, a ternary code error detector is provided to detect if the net positive polarity or if the net negative polarity exceed the selected limits. If either selected limit is exceeded, the error detector produces an error signal which can be used in any way desired, such as to switch to other multiplexing equipment, or to switch to other transmission lines, or to produce any sort of desired alarm.
Inventors
- 👤 J Smith
- 👤 J Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:03
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24; H04L1/245; H04L1/247
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
347 words
For use in a time-division multiplex, pulse-code modulation system using a ternary code, an error detector for indicating that the net positive ternary pulse count exceeds a selected limit and for indicating that the net negative ternary pulse count exceeds a selected limit, said error detector comprising: a. a first circuit adapted to be connected to said system for responding to positive ternary pulses; b. a second circuit adapted to be connected to said system for responding to negative ternary pulses; c. a counter having a positive input, a negative input, a plurality of normal outputs, and a plurality of inverted outputs; d. a positive counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a first signal in response to a selected positive count in said counter; e. a negative counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a second signal in response to a selected negative count in said counter; f. a positive control gate connected between said first circuit and said positive input of said counter for applying positive ternary pulses thereto, said positive control gate being connected to the output of said positive counter gate for blocking said positive ternary pulses in response to said first signal; g. a negative control gate connected between said second circuit and said negative input of said counter for applying negative ternary pulses thereto, said negative control gate being connected to the output of said negative counter gate for blocking said negative ternary pulses in response to said second signal; h. a positive error gate connected to said first circuit, said positive error gate being connected to said positive counter gate for producing an error signal in response to said first signal and a subsequently received positive ternary pulse; i. and a negative error gate connected to said second circuit, said negative error gate being connected to said negative counter gate for producing an error signal in response to said second signal and a subsequently received negative ternary pulse.
Claim 2
Dependent Claim
347 words
For use in a time-division multiplex, pulse-code modulation system using a ternary code, an error detector for indicating that the net positive ternary pulse count exceeds a selected limit and for indicating that the net negative ternary pulse count exceeds a selected limit, said error detector comprising: a. a first circuit adapted to be connected to said system for responding to positive ternary pulses; b. a second circuit adapted to be connected to said system for responding to negative ternary pulses; c. a counter having a positive input, a negative input, a plurality of normal outputs, and a plurality of inverted outputs; d. a positive counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a first signal in response to a selected positive count in said counter; e. a negative counter gate having a plurality of inputs respectively connected to selected ones of said counter outputs for producing a second signal in response to a selected negative count in said counter; f. a positive control gate connected between said first circuit and said positive input of said counter for applying positive ternary pulses thereto, said positive control gate being connected to the output of said positive counter gate for blocking said positive ternary pulses in response to said first signal; g. a negative control gate connected between said second circuit and said negative input of said counter for applying negative ternary pulses thereto, said negative control gate being connected to the output of said negative counter gate for blocking said negative ternary pulses in response to said second signal; h. a positive error gate connected to said first circuit, said positive error gate being connected to said positive counter gate for producing an error signal in response to said first signal and a subsequently received positive ternary pulse; i. and a negative error gate connected to said second circuit, said negative error gate being connected to said negative counter gate for producing an error signal in response to said second signal and a subsequently received negative ternary pulse.
Claim 3
Dependent Claim
40 words
The error detector of claim 1 wherein said first signal is produced in response to a positive count of three in said counter, and said second signal is produced in response to a negative count of four in said counter.
Claim 4
Dependent Claim
312 words
An improved error detector for use in a system having ternary pulses therein comprising: a. an input circuit adapted to be coupled to said system, said input circuit having a positive output for producing signals in response to positive ternary pulses and having a negative output for producing signals in response to negative ternary pulses; b. an up-down counter having a positive input, a negative input, and having 1, 1, 2, 2, 4, and 4 outputs; c. a first positive AND gate having at least three inputs respectively connected to 1, 2, and 4 outputs of said counter; d. a first negative AND gate having at least three inputs respectively connected to said 1, 2, and 4 outputs of said counter; e. a second positive AND gate having at least two inputs, one of said second positive AND gate inputs being connected to said positive output and the other of said second positive AND gate inputs being connected through an inverter to the output of said first positive AND gate; f. a second negative AND gate having at least two inputs, one of said second negative AND gate inputs being connected to said negative output and the other of said second negative AND gate inputs being connected through an inverter to the output of said first negative AND gate; g. a positive error AND gate having at least two inputs, one of said positive error AND gate inputs being connected to said positive output and the other of said positive error AND gate inputs being connected to said output of said first positive AND gate; h. and a negative error AND gate having at least two inputs, one of said negative error AND gate inputs being connected to said negative output and the other of said negative error AND gate inputs being connected to said output of said first negative AND gate.
Claim 5
Dependent Claim
312 words
An improved error detector for use in a system having ternary pulses therein comprising: a. an input circuit adapted to be coupled to said system, said input circuit having a positive output for producing signals in response to positive ternary pulses and having a negative output for producing signals in response to negative ternary pulses; b. an up-down counter having a positive input, a negative input, and having 1, 1, 2, 2, 4, and 4 outputs; c. a first positive AND gate having at least three inputs respectively connected to 1, 2, and 4 outputs of said counter; d. a first negative AND gate having at least three inputs respectively connected to said 1, 2, and 4 outputs of said counter; e. a second positive AND gate having at least two inputs, one of said second positive AND gate inputs being connected to said positive output and the other of said second positive AND gate inputs being connected through an inverter to the output of said first positive AND gate; f. a second negative AND gate having at least two inputs, one of said second negative AND gate inputs being connected to said negative output and the other of said second negative AND gate inputs being connected through an inverter to the output of said first negative AND gate; g. a positive error AND gate having at least two inputs, one of said positive error AND gate inputs being connected to said positive output and the other of said positive error AND gate inputs being connected to said output of said first positive AND gate; h. and a negative error AND gate having at least two inputs, one of said negative error AND gate inputs being connected to said negative output and the other of said negative error AND gate inputs being connected to said output of said first negative AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-14 | 1978-04-15 | 1978-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-14 | 1982-04-15 | 1982-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-14 | 1986-04-15 | 1986-10-15 | $7700.00 | Window Closed / Lapsed |