Patent US4176332A successfully refreshed from Google Patents.
US4176332A
Expired / Lapsed
US
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Frequency multiplier
Assignee: Motorola Solutions Inc
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Filing: 1977-11-18
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Granted: 1979-11-27
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Expires: 1997-11-18
Abstract
Abstract A signal at a frequency f 0 is coupled through matching circuitry to the input of a parametric frequency multiplier stage. Non-linearities in this stage generate harmonics of the frequency f 0 , including a desired harmonic k×f 0 , where k=2, 4, 6, 8... . Unique output coupling circuitry presents a high load impedance to the parametric multiplier at the frequency f 0 , thereby enhancing harmonic generation, and transforms the impedance to signals of frequency k×f 0 at the multiplier stage output to a desired value. The output coupling circuit includes two series connected transmission lines which couple between the output of the parametric multiplier stage and the multiplier output. A third transmission line, having an electrical length of one quarter wavelength at frequency f 0 , is connected as an open circuit shunt stub to the multiplier output, thereby effectively producing a short circuit thereat at f 0 . The combined electrical length of the series connected transmission lines is also one quarter wavelength at frequency f 0 thereby transforming the short at the multiplier output to a high impedance at the output of the parametric multiplier. The desired impedance transformation is accomplished by providing each of the series connected transmission lines with an appropriate characteristics impedance.
Inventors
- 👤 Peter Bachert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:39
CPC Classifications
H; H03; H03B; H03B19/00; H03B19/06; H03B19/14
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
306 words
A frequency multiplier circuit for receiving a signal of frequency f 0 and producing a signal of frequency k x f 0 , where k=2, 4, 6, 8 . . . , at a desired output impedance Z 0 , said multiplier circuit comprising: harmonic generating means adapted for receiving said signal of frequency f 0 and producing signals at frequency harmonics thereof, including a harmonic signal of frequency k×f 0 , the amplitude of said harmonic signals increasing with an increased signal at f 0 in said harmonic generating means, said harmonic generating means exhibiting an output impedance Z out '; coupling means for coupling said signal of frequency f 0 to said harmonic generating means; output loading means coupled to said harmonic generating means and providing a load circuit thereto, said output loading means comprising: (a) first and second series coupled transmission line means for coupling said harmonic generating means produced harmonic signals to the multiplier circuit output, each of said first and second transmission lines having predetermined characteristic impedances for transforming the impedance to signals of frequency k×f 0 at the input thereof to the desired output impedance Z 0 of said frequency multiplier, said first and second transmission lines having predetermined electrical lengths to provide a combined phase shift of 180° to signals of frequency (2n-1)×f 0 , where n=1, 2, 3 . . . ; and (b) third transmission line means having an electrical length of one quarter wavelength at frequencies (2n-1)×f 0 , where n=1, 2, 3 . . . , coupled to the output of said frequency multiplier such that a short at frequency f 0 is reflected thereto, whereby the short at frequency f 0 at the output of the multiplier circuit is transformed to a high impedance at f 0 to the output of said harmonic generator.
Claim 2
Dependent Claim
306 words
A frequency multiplier circuit for receiving a signal of frequency f 0 and producing a signal of frequency k x f 0 , where k=2, 4, 6, 8 . . . , at a desired output impedance Z 0 , said multiplier circuit comprising: harmonic generating means adapted for receiving said signal of frequency f 0 and producing signals at frequency harmonics thereof, including a harmonic signal of frequency k×f 0 , the amplitude of said harmonic signals increasing with an increased signal at f 0 in said harmonic generating means, said harmonic generating means exhibiting an output impedance Z out '; coupling means for coupling said signal of frequency f 0 to said harmonic generating means; output loading means coupled to said harmonic generating means and providing a load circuit thereto, said output loading means comprising: (a) first and second series coupled transmission line means for coupling said harmonic generating means produced harmonic signals to the multiplier circuit output, each of said first and second transmission lines having predetermined characteristic impedances for transforming the impedance to signals of frequency k×f 0 at the input thereof to the desired output impedance Z 0 of said frequency multiplier, said first and second transmission lines having predetermined electrical lengths to provide a combined phase shift of 180° to signals of frequency (2n-1)×f 0 , where n=1, 2, 3 . . . ; and (b) third transmission line means having an electrical length of one quarter wavelength at frequencies (2n-1)×f 0 , where n=1, 2, 3 . . . , coupled to the output of said frequency multiplier such that a short at frequency f 0 is reflected thereto, whereby the short at frequency f 0 at the output of the multiplier circuit is transformed to a high impedance at f 0 to the output of said harmonic generator.
Claim 3
Dependent Claim
18 words
The frequency multiplier circuit of claim 1 wherein said harmonic generating means comprises a parametric frequency multiplying device.
Claim 4
Dependent Claim
58 words
The frequency multiplier circuit of claim 1 wherein said harmonic generating means comprises: a semiconductor device having first, second and third terminals, said first terminal receiving said signal of frequency f 0 , said second terminal coupled to a reference potential and said third terminal for producing said harmonic frequency signals due to non-linearities in said semiconductor device.
Claim 5
Dependent Claim
64 words
The frequency multiplier circuit of claim 3 wherein said semiconductor device is a bipolar transistor having its emitter coupled to said first terminal, its base coupled to said second terminal and its collecter coupled to said third terminal and wherein said semiconductor non-linearities include the exponential voltage/current relationship of the emitter-base junction and variations in base-collector depletion capacitance as a function of base-collector voltage.
Claim 6
Dependent Claim
60 words
The frequency multiplier circuit of claim 1 wherein the source of said signal of frequency f 0 has an output impedance Z s , wherein said harmonic generating means has an input impedance Z in ' and wherein said coupling means includes means for matching said source impedance Z s to said harmonic generating means input impedance Z in '.
Claim 7
Dependent Claim
33 words
The frequency multiplier circuit of claim 5 wherein said coupling means further comprises input filter means for suppressing the coupling of signals at harmonic frequencies of f 0 to the harmonic generating means.
Claim 8
Dependent Claim
60 words
The frequency multiplier circuit of claim 4 wherein the source of said signal of frequency f 0 has an output impedance Z s , wherein said harmonic generating means has an input impedance Z in ' and wherein said coupling means includes means for matching said source impedance Z s to said harmonic generating means input impedance Z in '.
Claim 9
Dependent Claim
43 words
The frequency multiplier circuit of claim 7 wherein said coupling means further comprises input filter means for suppressing the coupling of signals at harmonic frequencies of f 0 from the source of said signal of frequency f 0 to the harmonic generating means.
Claim 10
Dependent Claim
45 words
The frequency multiplier circuit of claim 1, 4 or 6 wherein the output loading means further comprises impedance matching means for matching the output impedance Z out ' of said harmonic generating means to the input of said series coupled first and second transmission lines.
Claim 11
Dependent Claim
274 words
A frequency doubler circuit for receiving an input signal of frequency f 0 and producing an output signal of frequency 2×f 0 , and having an output impedance Z 0 , comprising: a parametric frequency multiplier means having an input for receiving said signal at frequency f 0 and an output for producing said signal f 0 and harmonics thereof including a signal of frequency 2×f 0 , said parametric multiplier having an output impedance Z out ', and coupling means coupled between the output of said parametric frequency multiplier and the output of said frequency doubler, said coupler means comprising: (a) first and second series coupled transmission line means for coupling said parametric frequency multiplier means produced harmonic signals to the frequency doubler circuit output, each of said first and second transmission lines having predetermined characteristic impedances for transforming the impedance to signals of frequency 2×f 0 at the input thereof to the desired output impedance Z 0 , of said frequency doubler, said first and second transmission lines having predetermined electrical lengths to provide a combined phase shift of 180° to signals of frequency (2n-1)×f 0 , where n=1, 2, 3 . . . ; and (b) third transmission line means having an electrical length of one quarter wavelength at frequencies (2n-1)×f 0 , where n=1, 2, 3 . . . , coupled to the output of said frequency doubler such that a short at frequency f 0 is reflected thereto; whereby the short at frequency f 0 at the output of the doubler circuit is transformed to a high impedance at f 0 to the output of said parametric frequency multiplier.
Claim 12
Dependent Claim
274 words
A frequency doubler circuit for receiving an input signal of frequency f 0 and producing an output signal of frequency 2×f 0 , and having an output impedance Z 0 , comprising: a parametric frequency multiplier means having an input for receiving said signal at frequency f 0 and an output for producing said signal f 0 and harmonics thereof including a signal of frequency 2×f 0 , said parametric multiplier having an output impedance Z out ', and coupling means coupled between the output of said parametric frequency multiplier and the output of said frequency doubler, said coupler means comprising: (a) first and second series coupled transmission line means for coupling said parametric frequency multiplier means produced harmonic signals to the frequency doubler circuit output, each of said first and second transmission lines having predetermined characteristic impedances for transforming the impedance to signals of frequency 2×f 0 at the input thereof to the desired output impedance Z 0 , of said frequency doubler, said first and second transmission lines having predetermined electrical lengths to provide a combined phase shift of 180° to signals of frequency (2n-1)×f 0 , where n=1, 2, 3 . . . ; and (b) third transmission line means having an electrical length of one quarter wavelength at frequencies (2n-1)×f 0 , where n=1, 2, 3 . . . , coupled to the output of said frequency doubler such that a short at frequency f 0 is reflected thereto; whereby the short at frequency f 0 at the output of the doubler circuit is transformed to a high impedance at f 0 to the output of said parametric frequency multiplier.
Claim 13
Dependent Claim
59 words
The frequency doubler circuit of claim 10 wherein said parametric frequency multiplier means comprises: a semiconductor device having first, second and third terminals, said first terminal receiving said signal of frequency f 0 , said second terminal coupled to a reference potential and said third terminal for producing said harmonic frequency signals due to non-linearities in said semiconductor device.
Claim 14
Dependent Claim
65 words
The frequency doubler circuit of claim 11 wherein said semiconductor device is a bipolar transistor having its emitter coupled to said first terminal, its base coupled to said second terminal and its collector coupled to said third terminal and wherein said semiconductor non-linearities include the exponential voltage/current relationship of the emitter-base junction and variation in the base-collector depletion capacitance as a function of base-collector voltage.
Claim 15
Dependent Claim
43 words
The frequency doubler circuit of claim 10 or 12 wherein the coupling means further comprises impedance matching means for matching the output impedance Z out ' of said parametric frequency multiplier to the input of said series coupled first and second transmission lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-11-26 | 1983-05-28 | 1983-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-11-26 | 1987-05-28 | 1987-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-11-26 | 1991-05-28 | 1991-11-27 | $7700.00 | Window Closed / Lapsed |