Frequency multiplier circuit

Claim 2

A frequency multiplier comprising: first, second, third and fourth transmission line center conductors each having means for capacitively coupling opposite center conductors ends to a common reference potential, said first and second center conductors being capacitively coupled to each other and said third and fourth center conductors being capacitively coupled to each other; and a semiconductor device responsive to an input signal at an input frequency and D.C. bias signals for generating an output signal at a frequency harmonically related to said input frequency, said device having a predetermined input and output impedance, said device having a first terminal coupled to said second center conductor, a second terminal coupled to said reference potential and a third terminal coupled to said third center conductor, said first and second center conductors being arranged to match said input impedance of said device at said input frequency, said third and fourth center conductors being mutually arranged to match said output impedance of said device at said desired signal frequency with said third conductor providing a relatively low impedance path to said reference potential at said input frequency and said fourth center conductor being resonant at said desired signal frequency.

Claim 3

A frequency multiplier according to claim 1, further including: means for coupling said input signal to said first center conductor; means for coupling said desired signal from said fourth center conductor; and means for coupling said D.C. bias signals to said first and third device terminals.

Claim 4

A frequency multiplier according to claim 1, wherein said first, second, third and fourth transmission line center conductors are coplanar conductive strips on one surface of a dielectric substrate having a conductive strip at said reference potential on a dielectric surface opposite said one surface.

Claim 5

A frequency multiplier according to claim 1, wherein said semiconDuctor device is a transistor.

Claim 6

A frequency multiplier according to claim 1, wherein said second center conductor is arranged to provide a relatively low impedance path to said reference potential for said desired signal.

Claim 7

A frequency multiplier according to claim 1, wherein said input and input device impedance is substantially determined by said input signal and said D.C. bias signals.

Claim 8

A frequency multipler comprising: first, second, third and fourth coplanar conductive strips on one surface of a dielectric substrate having a conductive strip at a reference potential on a dielectric surface opposite said one surface, each of said conductive strips having means for capacitively coupling opposite conductive strip ends to said reference potential conductive strip, said first and second conductive strips being capacitively coupled to each other and said third and fourth conductive strips being capacitively coupled to each other; and a transistor responsive to an input signal at an input frequency and D.C. bias signals for generating an output signal at a frequency harmonically related to said input frequency, said transistor having a predetermined input and output impedance, said transistor having a first terminal coupled to said second conductive strip, a second terminal coupled to said reference potential conductive strip and a third terminal coupled to said third conductive strips, said first and second conductive strips being mutually arranged to match said input impedance of said transistor at said input frequency, said third and fourth conductive strips being mutually arranged to match said output impedance of said transistor at said desired signal frequency with said third conductive strip providing a relatively low impedance path to said reference potential at said input frequency and said fourth conductive strip being resonant at said desired signal frequency.

Claim 9

A frequency multipler comprising: first, second, third and fourth coplanar conductive strips on one surface of a dielectric substrate having a conductive strip at a reference potential on a dielectric surface opposite said one surface, each of said conductive strips having means for capacitively coupling opposite conductive strip ends to said reference potential conductive strip, said first and second conductive strips being capacitively coupled to each other and said third and fourth conductive strips being capacitively coupled to each other; and a transistor responsive to an input signal at an input frequency and D.C. bias signals for generating an output signal at a frequency harmonically related to said input frequency, said transistor having a predetermined input and output impedance, said transistor having a first terminal coupled to said second conductive strip, a second terminal coupled to said reference potential conductive strip and a third terminal coupled to said third conductive strips, said first and second conductive strips being mutually arranged to match said input impedance of said transistor at said input frequency, said third and fourth conductive strips being mutually arranged to match said output impedance of said transistor at said desired signal frequency with said third conductive strip providing a relatively low impedance path to said reference potential at said input frequency and said fourth conductive strip being resonant at said desired signal frequency.

Claim 10

A frequency multiplier according to claim 7, wherein said input and output transistor impedance is substantially determined by said input signal and said D.C. bias signals.

Claim 11

An oscillator comprising: first, second and third transmission line center conductors each having means for capacitively coupling opposite center conductor ends to a reference potential, said second and third center conductors being capacitively coupled to each other; a semiconductive device responsive to D.C. bias signals for generating an input signal at an input frequency and a desired signal at a frequency harmonically related to said input frequency, said device having a predetermined input and output impedance, said device having a first terminal coupled to said first center conductor, a second terminal coupled to said reference potential and a third terminal coupled to said third center conductor, said second and third center conductors being mutually arranged to match said output impedance of said device at said desired signal frequency with said second center conductor providing a relatively low impedance path to said reference potential at said input frequency and said third center conductor being resonant at said desired signal frequency; and means for providing a path for signals at said input frequency from said first center conductor to said second center conductor.

Claim 12

An oscillator comprising: first, second and third transmission line center conductors each having means for capacitively coupling opposite center conductor ends to a reference potential, said second and third center conductors being capacitively coupled to each other; a semiconductive device responsive to D.C. bias signals for generating an input signal at an input frequency and a desired signal at a frequency harmonically related to said input frequency, said device having a predetermined input and output impedance, said device having a first terminal coupled to said first center conductor, a second terminal coupled to said reference potential and a third terminal coupled to said third center conductor, said second and third center conductors being mutually arranged to match said output impedance of said device at said desired signal frequency with said second center conductor providing a relatively low impedance path to said reference potential at said input frequency and said third center conductor being resonant at said desired signal frequency; and means for providing a path for signals at said input frequency from said first center conductor to said second center conductor.

Claim 13

An oscillator according to claim 9, further including: means for coupling said D.C. bias signals to said first and third device terminals; and means for coupling said output signal from said third center conductor.

Claim 14

An oscillator according to claim 9, wherein said means for providing a path for said input signals at said input frequency from said first center conductor to said second center conductor include capacitor means having one terminal coupled to said first center conductor and a second terminal coupled to said second center conductor, said capacitor means being arranged with said first and second center conductors to match said input impedance of said device at said input sIgnal frequency.

Claim 15

An oscillator according to claim 9, wherein said input and output device impedance is determined by said input signal and said D.C. bias signals.