US4174537A — Time-shared, multi-phase memory accessing system …

Claim 1

Independent Claim 308 words

In a data processing system, the combination comprising: a memory partitioned into a plurality of individually addressable memory portions, the accessing time of each memory portion requiring at least a plurality of operating cycles of said data processing system; addressing means coupled to said memory and responsive to an applied address for initiating accessing of selected locations in a plurality of different memory portions over a plurality of consecutively occurring operating cycles in a manner such that the accessing of only a particular selected one of said memory portions is initiated during an operating cycle; data accumulation means capable of simultaneously storing data read out from a plurality of said memory portions; memory output means coupled to said memory and operative during a read operation for receiving data read out from each addressed selected location of a memory portion as it becomes available and operative during each of a plurality of said operating cycles for storing a predetermined portion of the received data from a selected one of said memory portions in a different designated location of said accumulation means until all of the predetermined portions of the received data read out from the addressed selected locations of said memory are simultaneously stored in said accumulation means; said memory output means including error checking means for detecting the occurrence of a plurality of different types of errors which may occur in data read out from an addressed selected locaton of a memory portion and for producing error patterns corresponding thereto; and error logging means coupled to said error checking means and responsive thereto for simultaneously storing indications of the occurrence of a plurality of different types of detected errors and for also storing the corresponding error pattern of a first predetermined type of error on a predetermined priority basis over that of a second predetermined type of error.

Claim 2

Dependent Claim 308 words

In a data processing system, the combination comprising: a memory partitioned into a plurality of individually addressable memory portions, the accessing time of each memory portion requiring at least a plurality of operating cycles of said data processing system; addressing means coupled to said memory and responsive to an applied address for initiating accessing of selected locations in a plurality of different memory portions over a plurality of consecutively occurring operating cycles in a manner such that the accessing of only a particular selected one of said memory portions is initiated during an operating cycle; data accumulation means capable of simultaneously storing data read out from a plurality of said memory portions; memory output means coupled to said memory and operative during a read operation for receiving data read out from each addressed selected location of a memory portion as it becomes available and operative during each of a plurality of said operating cycles for storing a predetermined portion of the received data from a selected one of said memory portions in a different designated location of said accumulation means until all of the predetermined portions of the received data read out from the addressed selected locations of said memory are simultaneously stored in said accumulation means; said memory output means including error checking means for detecting the occurrence of a plurality of different types of errors which may occur in data read out from an addressed selected locaton of a memory portion and for producing error patterns corresponding thereto; and error logging means coupled to said error checking means and responsive thereto for simultaneously storing indications of the occurrence of a plurality of different types of detected errors and for also storing the corresponding error pattern of a first predetermined type of error on a predetermined priority basis over that of a second predetermined type of error.

Claim 3

Dependent Claim 32 words

The invention in accordance with claim 1, wherein said error logging means includes means for storing an indication of the occurrence of a particular type of error more than a single time.

Claim 4

Dependent Claim 25 words

The invention in accordance with claim 1, wherein said error logging means includes means for storing the memory address corresponding to the stored error pattern.

Claim 5

Dependent Claim 31 words

The invention in accordance with claim 3, wherein said error logging means is responsive to an applied signal for transmitting the stored error information and corresponding address to said accumulation means.

Claim 6

Dependent Claim 19 words

The invention in accordance with claim 4, wherein said error logging means is cleared after transmitting the stored information.

Claim 7

Dependent Claim 96 words

The invention in accordance with claim 1, additionally including: memory input means operative during a write operation for receiving input write data, predetermined portions of which are to be written into selected locations of a plurality of said memory portions as determined by said addressing means, said memory input means being operative during an operating cycle to provide for writing a selected respective portion of said input write data along with an error check code into only the particular one of said memory portions whose accessing is initiated during an operating cycle by said addressing means.

Claim 8

Dependent Claim 84 words

The invention in accordance with claim 6, wherein said error check code and said error checking means are chosen so that said error checking means provides error patterns indicating whether a detected error is a single or a multiple bit error, and wherein said error logging provides for simultaneously storing indications of the occurrence of both a single bit and a multiple bit error while giving priority to the storing of a multiple bit error pattern over that of a single bit error pattern.

Claim 9

Dependent Claim 35 words

The invention in accordance with claim 7, wherein said error logging means also gives priority to the first occurring error of a particular type over that of a later occurring error of the same type.

Claim 10

Dependent Claim 33 words

The invention in accordance with claim 7, wherein said error logging means includes means for storing an indication of the duplicate occurrence of a single bit error and of a multiple bit error.

Claim 11

Dependent Claim 46 words

The invention in accordance with claim 6, wherein said memory output means also includes error correcting means responsive to the error patterns produced by said error checking means for correcting a single bit error occurring in the received data prior to storing in said accumulation means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1982-11-12	1983-05-14	1983-11-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1986-11-12	1987-05-14	1987-11-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1990-11-12	1991-05-14	1991-11-13	$7700.00	Window Closed / Lapsed

Time-shared, multi-phase memory accessing system having automatically updatable error logging means

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