Patent US4170741A successfully refreshed from Google Patents.
US4170741A
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High speed CMOS sense circuit for semiconductor memories
Assignee: Micron Technology Inc
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Filing: 1978-03-13
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Granted: 1979-10-09
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Expires: 1998-03-13
Abstract
Abstract A high speed sensing circuit is described incorporating complementary metal oxide semiconductor field effect transistor circuitry for sensing, amplifying and storing a signal indicative of the polarity of the difference voltage across two load elements. The load elements may be a pair of variable threshold transistors.
Inventors
- 👤 David W. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:21
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C16/04; G11C16/0466; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
419 words
A CMOS memory sense circuit for comparing a first and second voltage comprising: first through tenth field effect transistors each having a gate, source and drain electrode, said first through fourth and said sixth through ninth transistors having a P-type channel, said fifth and tenth transistors having an N-type channel, the source electrode of said first and sixth transistors coupled to the positive terminal of a first voltage supply, the drain electrode of said first transistor coupled to the source electrode of said second transistor, the drain electrode of said second transistor coupled to the source electrode of said third transistor, the drain electrode of said third transistor coupled to the source electrode of said fourth transistor, the drain electrode of said fourth transistor coupled to the drain electrode of said fifth transistor and to the gate electrode of said seventh and tenth transistors, the source electrode of said fifth and tenth transistors coupled to the negative terminal of said first voltage supply, the drain electrode of said sixth transistor coupled to the source electrode of said seventh transistor, the drain electrode of said seventh transistor coupled to the source electrode of said eighth transistor, the drain electrode of said eighth transistor coupled to the source electrode of said ninth transistor, the drain electrode of said ninth transistor coupled to the drain electrode of said tenth transistor and to the gate electrode of said second and fifth transistors, the gate electrode of said third transistor coupled to a means for applying said first voltage, the gate electrode of said eighth transistor coupled to a means for applying said second voltage, first through fourth control signals, first means coupled and responsive to said first control signal for coupling the gate electrode of said third and eighth transistors to said positive terminal of said first voltage supply, second means coupled and responsive to said second control signal for coupling the source electrode of said third transistor to the gate electrode of said eighth transistor, third means coupled and responsive to said second control signal for coupling the source electrode of said eighth transistor to the gate electrode of said third transistor, the gate electrode of said first, fourth, sixth and ninth transistors coupled to said third control signal for controlling the conduction of said first, fourth, sixth and ninth transistors, and fourth means coupled and responsive to said fourth control signal for coupling the drain electrode of said fourth and ninth transistors to the negative terminal of said first voltage supply.
Claim 2
Dependent Claim
419 words
A CMOS memory sense circuit for comparing a first and second voltage comprising: first through tenth field effect transistors each having a gate, source and drain electrode, said first through fourth and said sixth through ninth transistors having a P-type channel, said fifth and tenth transistors having an N-type channel, the source electrode of said first and sixth transistors coupled to the positive terminal of a first voltage supply, the drain electrode of said first transistor coupled to the source electrode of said second transistor, the drain electrode of said second transistor coupled to the source electrode of said third transistor, the drain electrode of said third transistor coupled to the source electrode of said fourth transistor, the drain electrode of said fourth transistor coupled to the drain electrode of said fifth transistor and to the gate electrode of said seventh and tenth transistors, the source electrode of said fifth and tenth transistors coupled to the negative terminal of said first voltage supply, the drain electrode of said sixth transistor coupled to the source electrode of said seventh transistor, the drain electrode of said seventh transistor coupled to the source electrode of said eighth transistor, the drain electrode of said eighth transistor coupled to the source electrode of said ninth transistor, the drain electrode of said ninth transistor coupled to the drain electrode of said tenth transistor and to the gate electrode of said second and fifth transistors, the gate electrode of said third transistor coupled to a means for applying said first voltage, the gate electrode of said eighth transistor coupled to a means for applying said second voltage, first through fourth control signals, first means coupled and responsive to said first control signal for coupling the gate electrode of said third and eighth transistors to said positive terminal of said first voltage supply, second means coupled and responsive to said second control signal for coupling the source electrode of said third transistor to the gate electrode of said eighth transistor, third means coupled and responsive to said second control signal for coupling the source electrode of said eighth transistor to the gate electrode of said third transistor, the gate electrode of said first, fourth, sixth and ninth transistors coupled to said third control signal for controlling the conduction of said first, fourth, sixth and ninth transistors, and fourth means coupled and responsive to said fourth control signal for coupling the drain electrode of said fourth and ninth transistors to the negative terminal of said first voltage supply.
Claim 3
Dependent Claim
17 words
The CMOS memory sense circuit of claim 1 wherein said first means includes two field effect transistors.
Claim 4
Dependent Claim
17 words
The CMOS memory sense circuit of claim 1 wherein said second means includes a field effect transistor.
Claim 5
Dependent Claim
17 words
The CMOS memory sense circuit of claim 1 wherein said third means includes a field effect transistor.
Claim 6
Dependent Claim
17 words
The CMOS memory sense circuit of claim 1 wherein said fourth means includes two field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-08 | 1983-04-09 | 1983-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-08 | 1987-04-09 | 1987-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-08 | 1991-04-09 | 1991-10-09 | $7700.00 | Window Closed / Lapsed |