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US4169746A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making silicon on sapphire transistor utilizing predeposition of leads

Assignee: RCA Corp
•
Filing: 1978-08-02
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Granted: 1979-10-02
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Expires: 1998-08-02
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Abstract

Abstract The integrated circuit is manufactured upside down relative to conventional silicon-on-sapphire (SOS) processing techniques for manufacturing field effect transistors. First a conductive pattern, typically of a refractory metal, is deposited and defined on an insulating substrate, such as sapphire, and then silicon transistors are formed over the conductive pattern. Using the process, a masking step, namely the contact definition mask, used in conventional SOS manufacture, is eliminated.

Inventors

  • 👤 Alfred C. Ipri
  • 👤 Joseph H. Scott, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 16:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6758; H10D30/6759; H10D30/6704; H10D30/6713; H10D86/00; H10D86/01; H10D86/03; H10P; H10P14/00; H10P14/40; H10P14/412; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H10W70/692; Y; Y10; Y10S; Y10S148/00; Y10S148/147; Y10S148/15

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 138 words
A method of making an integrated circuit structure comprising: (a) selecting an insulating body upon which a single crystal semiconductor device may be epitaxially deposited; (b) forming a series of conductors on a surface of said body; (c) epitaxially depositing semiconductor material on the exposed portions of said body and over said conductors; (d) defining said semiconductor material into transistors overlying said body and into first conductive regions overlying said conductors; (e) forming insulating layers over said transistors and first conductive regions; (f) forming second conductive gate regions over said insulating layers overlying said transistors while simultaneously forming conductive crossovers overlying said insulating layers which overlie said first conductive region; and (g) adding impurities to said transistors in order to form a source and drain in the area of said transistors which do not overlie said gate regions.
Claim 2
Independent Claim 138 words
A method of making an integrated circuit structure comprising: (a) selecting an insulating body upon which a single crystal semiconductor device may be epitaxially deposited; (b) forming a series of conductors on a surface of said body; (c) epitaxially depositing semiconductor material on the exposed portions of said body and over said conductors; (d) defining said semiconductor material into transistors overlying said body and into first conductive regions overlying said conductors; (e) forming insulating layers over said transistors and first conductive regions; (f) forming second conductive gate regions over said insulating layers overlying said transistors while simultaneously forming conductive crossovers overlying said insulating layers which overlie said first conductive region; and (g) adding impurities to said transistors in order to form a source and drain in the area of said transistors which do not overlie said gate regions.
Claim 3
Dependent Claim 20 words
The method of claim 1 wherein said series of conductors is formed by chemical vapor deposition of a refractory metal.
Claim 4
Dependent Claim 16 words
The method of claim 2 wherein said semiconductor material is epitaxially deposited by pyrolytically decomposing silane.
Claim 5
Dependent Claim 20 words
The method of claim 3 wherein said impurities are added by diffusion impurities forming doped oxide into said semiconductor material.
Claim 6
Dependent Claim 33 words
The method of claim 1 further comprising adding impurities of a second type to form transistors in order to form an integrated circuit structure having both P channel transistors and N channel transistors.

References Cited (Backward Citations)

US3258663A Cited
US3385731A Cited
US3191061A Cited
US3304469A Cited
US3460240A Cited
US3405331A Cited
US3616527A Cited
US3872492A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-10-01 1983-04-02 1983-10-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-10-01 1987-04-02 1987-10-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-10-01 1991-04-02 1991-10-02 $7700.00 Window Closed / Lapsed

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