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US4168997A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer

Assignee: National Semiconductor Corp
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Filing: 1978-10-10
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Granted: 1979-09-25
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Expires: 1998-10-10
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Abstract

Abstract In an integrated circuit structure a subsurface isolation layer is doped by diffusion during wafer processing. A substrate is first doped by ion implantation to create surface layer of the opposite conductivity type. Where substrate connections are to be created a heavier deposit of dopant is established using an impurity that will confer conductivity of the same polarity as the substrate. The wafer is then overgrown with an intrinsic layer that will be subsequently doped by diffusion of the ion implanted dopant. Then conventional integrated circuit processing is employed using buried conductive layers, epitaxy, isolation and device diffusion. The transistors thus produced can be designed to have isolation or substrate connected collectors as determined by the substrate surface doping.

Inventors

  • 👤 James B. Compton

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 21:58
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P30/202; H10P30/204; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/921

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 261 words
A semiconductor integrated circuit process comprising the steps: providing a semiconductor substrate wafer having one conductivity type; ion implanting a first impurity of said one conductivity type into a first group of selected regions of the surface of said substrate wafer; ion implanting a second impurity into said surface of said substrate wafer, said second impurity being of material capable of doping said semiconductor to a conductivity type opposite to said one conductivity type and in a concentration substantially lower than that of said first impurity said first and second impurities having a higher diffusion coefficient than the substrate impurity; growing a first substantially intrinsic epitaxial layer of semiconductor on said substrate wafer; depositing a third impurity into the surface of said first epitaxial layer in a second group of selected regions, said third impurity being capable of imparting said one conductivity type to said semiconductor, said second group of selected regions including regions in registry with said first group of selected regions; growing a second epitaxial layer of semiconductor on said first epitaxial layer, said second epitaxial layer having said one conductivity type; and forming isolation diffusions in said second epitaxial layer using an impurity that is capable of imparting said second conductivity type to said semiconductor and extending completely through said second epitaxial layer, whereby said diffusion causes said second impurity to dope said first epitaxial layer and causes said first and third impurities to dope said first epitaxial layer so that said first and third impurities span said first epitaxial layer in said first group of selected regions.
Claim 2
Dependent Claim 261 words
A semiconductor integrated circuit process comprising the steps: providing a semiconductor substrate wafer having one conductivity type; ion implanting a first impurity of said one conductivity type into a first group of selected regions of the surface of said substrate wafer; ion implanting a second impurity into said surface of said substrate wafer, said second impurity being of material capable of doping said semiconductor to a conductivity type opposite to said one conductivity type and in a concentration substantially lower than that of said first impurity said first and second impurities having a higher diffusion coefficient than the substrate impurity; growing a first substantially intrinsic epitaxial layer of semiconductor on said substrate wafer; depositing a third impurity into the surface of said first epitaxial layer in a second group of selected regions, said third impurity being capable of imparting said one conductivity type to said semiconductor, said second group of selected regions including regions in registry with said first group of selected regions; growing a second epitaxial layer of semiconductor on said first epitaxial layer, said second epitaxial layer having said one conductivity type; and forming isolation diffusions in said second epitaxial layer using an impurity that is capable of imparting said second conductivity type to said semiconductor and extending completely through said second epitaxial layer, whereby said diffusion causes said second impurity to dope said first epitaxial layer and causes said first and third impurities to dope said first epitaxial layer so that said first and third impurities span said first epitaxial layer in said first group of selected regions.
Claim 3
Dependent Claim 35 words
The process of claim 1 wherein said first group of selected regions includes those regions intended to accommodate substrate connected transistors in said integrated circuit and those regions intended to lie under wafer scribe lines.
Claim 4
Dependent Claim 26 words
The process of claim 2 wherein said one conductivity type is n type, said second impurity is boron, and said first and third impurities are phosphorus.
Claim 5
Dependent Claim 159 words
In the process of fabricating a subsurface isolation layer in an integrated circuit wherein said isolation layer is spanned in selected regions by buried layers, the steps comprising: ion implanting a first conductivity type impurity into said selected regions of the surface of a semiconductor substrate of said first type impurity; ion implanting a second impurity of opposite conductivity type into the surface of said semiconductor substrate said first and second impurities having a higher diffusion coefficient than the substrate impurity and wherein the nature and amount of said first impurity are selected to produce a greater concentration in the semiconductor than said second impurity; growing a substantially intrinsic epitaxial layer of semiconductor over the surface of said semiconductor substrate; and processing said semiconductor substrate to diffuse said second impurity through said epitaxial layer to determine the conductivity type thereof and to diffuse said first impurity through said epitaxial layer to determine the conductivity thereof above said selected regions.
Claim 6
Dependent Claim 159 words
In the process of fabricating a subsurface isolation layer in an integrated circuit wherein said isolation layer is spanned in selected regions by buried layers, the steps comprising: ion implanting a first conductivity type impurity into said selected regions of the surface of a semiconductor substrate of said first type impurity; ion implanting a second impurity of opposite conductivity type into the surface of said semiconductor substrate said first and second impurities having a higher diffusion coefficient than the substrate impurity and wherein the nature and amount of said first impurity are selected to produce a greater concentration in the semiconductor than said second impurity; growing a substantially intrinsic epitaxial layer of semiconductor over the surface of said semiconductor substrate; and processing said semiconductor substrate to diffuse said second impurity through said epitaxial layer to determine the conductivity type thereof and to diffuse said first impurity through said epitaxial layer to determine the conductivity thereof above said selected regions.
Claim 7
Dependent Claim 14 words
The process of claim 4 wherein said layer is grown without deliberate impurity doping.
Claim 8
Dependent Claim 21 words
The process of claim 5 wherein said semiconductor is silicon, said first impurity is phosphorus, and said second impurity is boron.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-09-24 1983-03-26 1983-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-09-24 1987-03-26 1987-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-09-24 1991-03-26 1991-09-25 $7700.00 Window Closed / Lapsed

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