Patent US4167778A successfully refreshed from Google Patents.
US4167778A
Expired / Lapsed
US
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Invalid instruction code detector
Assignee: Unisys Corp
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Filing: 1978-01-30
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Granted: 1979-09-11
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Expires: 1998-01-30
Abstract
Abstract A read-only memory, adapted to be addressed by the operation code portion of a computer instruction word, stores at addressable locations therein a flag indicating whether a particular combination of operation code bits is a valid combination.
Inventors
- 👤 Ralph E. Sipple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/22; G06F9/226
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
321 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instruction wherein fewer than 2 N possible different operation codes are defined as valid, the improved method of indicating the validity of each of said operation codes of each of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary one if said corresponding operation code is defined as valid and a binary zero if said corresponding operation code is not defined as valid; temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is valid if and only if said accessing revealed that said flag bit corresponding to said operation code is a binary one; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary one; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 2
Dependent Claim
321 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instruction wherein fewer than 2 N possible different operation codes are defined as valid, the improved method of indicating the validity of each of said operation codes of each of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary one if said corresponding operation code is defined as valid and a binary zero if said corresponding operation code is not defined as valid; temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is valid if and only if said accessing revealed that said flag bit corresponding to said operation code is a binary one; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary one; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 3
Dependent Claim
323 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instructions wherein fewer than 2 N possible different operation codes are defined as valid, the improved method for indicating the invalidity of one of said operation codes contained within one of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary one if said corresponding operation code is defined as valid and a binary zero if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is invalid if and only if said accessing reveals that said flag bit corresponding to said operation code is a binary zero; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary one; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 4
Dependent Claim
323 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instructions wherein fewer than 2 N possible different operation codes are defined as valid, the improved method for indicating the invalidity of one of said operation codes contained within one of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary one if said corresponding operation code is defined as valid and a binary zero if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is invalid if and only if said accessing reveals that said flag bit corresponding to said operation code is a binary zero; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary one; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 5
Dependent Claim
322 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instruction wherein fewer than 2 N possible different operation codes are defined as valid, the improved method of indicating the validity of each of said operation codes of each of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary zero if said corresponding operation code is defined as valid and a binary one if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for exectuion by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is valid if and only if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 6
Dependent Claim
322 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instruction wherein fewer than 2 N possible different operation codes are defined as valid, the improved method of indicating the validity of each of said operation codes of each of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary zero if said corresponding operation code is defined as valid and a binary one if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for exectuion by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is valid if and only if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 7
Dependent Claim
323 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instructions wherein fewer than 2 N possible different operation codes are defined as valid, the improved method for indicating the invalidity of one of said operation codes contained within one of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary zero if said corresponding operation code is defined as valid and a binary one if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is invalid if and only if said accessing reveals that said flag bit corresponding to said operation code is a binary one; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; and g. repeating steps b through f for each one of said series of computer instructions.
Claim 8
Dependent Claim
323 words
In a digital computer whose computations are controlled through the execution of a series of computer instructions each containing one of 2 N operation codes which are defined by N binary digits of said computer instructions wherein fewer than 2 N possible different operation codes are defined as valid, the improved method for indicating the invalidity of one of said operation codes contained within one of said computer instructions within said series of computer instructions comprising: a. storing within a read-only memory of capacity 2 N addressable bits, a flag bit corresponding to each of said 2 N possible different operation codes wherein said flag bit is a binary zero if said corresponding operation code is defined as valid and a binary one if said corresponding operation code is not defined as valid; b. temporarily storing one of said series of computer instructions currently scheduled for execution by said digital computer; c. decoding said operation code of said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer to generate an address of said read-only memory; d. accessing said flag bit within said read-only memory at said generated address corresponding to said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer; e. signaling said digital computer that said operation code within said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer is invalid if and only if said accessing reveals that said flag bit corresponding to said operation code is a binary one; f. executing said temporarily stored one of said series of computer instructions currently scheduled for execution by said digital computer if said accessing revealed that said flag bit corresponding to said operation code is a binary zero; and g. repeating steps b through f for each one of said series of computer instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-10 | 1983-03-12 | 1983-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-10 | 1987-03-12 | 1987-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-10 | 1991-03-12 | 1991-09-11 | $7700.00 | Window Closed / Lapsed |