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US4167731A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrating code converter

Assignee: US Philips Corp
•
Filing: 1978-05-26
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Granted: 1979-09-11
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Expires: 1998-05-26
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Abstract

Abstract Arrangement for converting a differential code into an absolute code which comprises a non-recursive interpolating digital filter, to which input code words are applied, with a sampling frequency f s , for supplying auxiliary code words occurring with an increased sampling frequency mf s , and a digital intergrator for converting the auxiliary code words into output code words, also with a sampling frequency mf s .

Inventors

  • 👤 Ludwig D. J. Eggermont

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 23:11
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/3002; H03M7/3044

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 166 words
A circuit arrangement for converting a sequence of digital input code words occurring with a first sampling frequency (F s ) and representative of changes in the instantaneous amplitude of a data signal in the form of a differential code into a sequence of output code words occurring with a second, higher sampling frequency (mf s ) and representative of the instantaneous amplitude of the data signal in the form of an absolute code, comprising: a non-recursive interpolating digital filter; means to apply input code words applied to said filter; means to output from said filter a sequence of digital auxiliary code words occurring with said second sampling frequency (mf s ) and which are also representative of changes in the instantaneous amplitude of the data signal; and a digital integrator for converting said auxiliary code words into said output code words; said digital integrator comprising: a cascade arrangement of m delay sections which each realize a delay over a period of time 1/mf s .
Claim 2
Dependent Claim 166 words
A circuit arrangement for converting a sequence of digital input code words occurring with a first sampling frequency (F s ) and representative of changes in the instantaneous amplitude of a data signal in the form of a differential code into a sequence of output code words occurring with a second, higher sampling frequency (mf s ) and representative of the instantaneous amplitude of the data signal in the form of an absolute code, comprising: a non-recursive interpolating digital filter; means to apply input code words applied to said filter; means to output from said filter a sequence of digital auxiliary code words occurring with said second sampling frequency (mf s ) and which are also representative of changes in the instantaneous amplitude of the data signal; and a digital integrator for converting said auxiliary code words into said output code words; said digital integrator comprising: a cascade arrangement of m delay sections which each realize a delay over a period of time 1/mf s .
Claim 3
Dependent Claim 156 words
The circuit arrangement as claimed in claim 1, wherein said digital integrator comprises: an input terminal which receives a sequence of digital auxiliary code words occurring with said second sampling frequency (mf s ) and which words are representative of changes in the instantaneous amplitude of the data signal; an adding means in said digital integrator having as a first input said auxiliary code words; an output of said adding means which supplies an output terminal with absolute code words; a feedback circuit comprising: at least one delay section; a multiplier; means to supply the output of said adder to said delay section and sequentially to said multiplier; said multiplier multiplying said absolute code words by a factor les than 1; the output of said multiplier being fedback as a second input to said adding means; such that said delay section and said multiplying device process only the input code words, thus utilizing minimal storage capacity.

References Cited (Backward Citations)

US3596267A Cited
US3633170A Cited
US3707712A Cited
US3906400A Cited
US4002981A Cited
US4035724A Cited
US3987288A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-09-10 1983-03-12 1983-09-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-09-10 1987-03-12 1987-09-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-09-10 1991-03-12 1991-09-11 $7700.00 Window Closed / Lapsed

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