Zero phase switching for multi-phase systems

Claim 2

A multi-phase, zero phase control apparatus comprising: supply terminal means for the supply of multi-phase power; load terminal means for connection to a load; multi-line connecting means for connecting said supply terminal means to said load means, said multi-line connecting means having at least first and second switch means in respective first and second lines of said multi-line connecting means; and, first and second switch control means for energizing said first and second switch means respectively to conduct current, beginning at substantially the zero point in the current cycle, to the load means, said first and second switch control means having synchronization means connected between said multi-line connecting means and said first and second switch control means to insure that said first and second switch control means are synchronized to the current supplied to said load terminal means regardless of the conductive state of said first and second switch means.

Claim 3

The apparatus of claim 1 wherein said first switch control means comprises a first resistor connected between said synchronization means and said first line, a first transistor having an emitter and a base connected across said first resistor and a collector, said emitter being connected to said first line, a second transistor having a base connected to said base of said first transistor, a collector and an emitter, a third transistor having a base connected to said first line, an emitter connected to the emitter of said second transistor and a collector connected to the collector of said first transistor, means connecting said collectors of said second and third transistors across a source of direct current potential, a capacitor, means connecting said capacitor across said base and collector of said third transistor and across said source of direct current potential, and a gating circuit connected to said capacitor of said first switch means for turning on said first switch means at substantially the zero point in the current cycle of the current controlled by said first switch means.

Claim 4

The apparatus of claim 1 wherein said synchronization means comprises a delta connected resistive network connected between said multi-line connecting means and said first and second switch control means.

Claim 5

The apparatus of claim 1 wherein said supply terminal means comprises at least first, second and third supply terminals, said load terminal means comprises at least first, second and third load terminals, said multi-line connecting means comprising at least first and second conductors and third conductor means, said first switch means being in said first conductor for connecting said first supply terminal to said first load terminal, said second switch means being in said second conductor for connecting said second supply terminal to said second load terminal and said third conductor means connecting said third supply terminal to said third load terminal.

Claim 6

The apparatus of claim 4 wherein said synchronization means comprises a delta connected resistive network.

Claim 7

The apparatus of claim 5 wherein said delta connected resistive network comprises a first resistor connected from said first switch control means to a junction between said second switch means and said second load terminal, a second resistor connected from said second switch control means to a junction between said first switch means and said first load terminal, a third resistor connected from a junction of said first resistor and said first switch control means to said third conductor means and a fourth resistor connected from a junction of said second resistor and said second switch control means to said third conductor means.

Claim 8

The apparatus of claim 6 wherein said first switch control means comprises a fifth resistor connected between said first resistor and said first conductor, a first transistor having an emitter and a base connected across said fifth resistor and a collector, said emitter being connected to said first conductor, a second transistor having a base connected to said base of said first transistor, a collector and an emitter, a third transistor having a base connected to said first conductor, an emitter connected to the emitter of said second transistor and a collector connected to the collector of said first transistor, means connecting said collectors of said second and third transistors across a source of direct current potential, a capacitor, means connecting said capacitor across said base and collector of said third transistor and across said source of direct current potential, and a gating circuit connected to said capacitor and said first switch means for turning on said first switch means at substantially the zero point in the current cycle of the current controlled by said first switch means.

Claim 9

The apparatus of claim 6 wherein said first switch control means comprises a first switch control means resistor connected from said first connector to said first resistor, a first gating circuit connected to said first switch means and a first zero sensing circuit connected between said first switch control means resistor and said first gating circuit, and said second switch control means comprises a second switch control means resistor connected to said second resistor, a second gating circuit connected to said second switch means and a second zero sensing circuit connected between said second switch control means resistor and said second gating circuit.

Claim 10

The apparatus of claim 8 wherein said first zero sensing means comprises a first zero sensor for sensing the zero point in the current cycle of the current through said first switch control means resistor and a first time proportioning condition responsive means for insuring that the first switch means will not be turned on until both the zero point in the current cycle of the current in the first conductor has been substantially attained and a time proportioning signal from said first time proportioning condition responsive means has been received and the second zero sensing means comprises a second zero sensor for sensing the zero point in the current cycle of the current through said second switch control means resistor and a second time proportioning condition responsive means for insuring that the second switch means will not be turned on until both the zero point in the current cycle of the current in the second conductor has been substantially attained and a time proportioning signal from said second time proportioning condition responsive means has been received.

Claim 11

The apparatus of claim 9 wherein said first and second switch means comprises respective first and second solid state switches having respective first and second gates connected to said respective first and second gating circuits.

Claim 12

A three phase, zero phase control apparatus comprising: first, second and third supply terminals for the supply of three phase power; first, second and third load terminals for connection to a three phase load; first connecting means for connecting said first supply terminal to said first load terminal, second connecting means for connecting said second supply terminal to said second load terminal, and third connecting means for connecting said third supply terminal to said third load terminal, at least said first and second connecting means having respective first and second switch means therein; and, first and second switch control means for energizing said first and second switch means to conduct current, beginning at the zero point of the current cycle, to the load means, said first and second switch control means having synchronization means connected between said first, second and third connecting means and said first and second switch control means to insure that the first and second switch control means are synchronized to the current supplied to said first, second and third load terminals regardless of the conductive state of said first and second switch means.

Claim 13

A three phase, zero phase control apparatus comprising: first, second and third supply terminals for the supply of three phase power; first, second and third load terminals for connection to a three phase load; first connecting means for connecting said first supply terminal to said first load terminal, second connecting means for connecting said second supply terminal to said second load terminal, and third connecting means for connecting said third supply terminal to said third load terminal, at least said first and second connecting means having respective first and second switch means therein; and, first and second switch control means for energizing said first and second switch means to conduct current, beginning at the zero point of the current cycle, to the load means, said first and second switch control means having synchronization means connected between said first, second and third connecting means and said first and second switch control means to insure that the first and second switch control means are synchronized to the current supplied to said first, second and third load terminals regardless of the conductive state of said first and second switch means.

Claim 14

The apparatus of claim 11 wherein said first switch control means comprises a first resistor connected between said synchronization means and said first line, a first transistor having an emitter and a base connected across said first resistor and a collector, said emitter being connected to said first line, a second transistor having a base connected to said base of said first transistor, a collector and an emitter, a third transistor having a base connected to said first line, an emitter connected to the emitter of said second transistor and a collector connected to the collector of said first transistor, means connecting said collectors of said second and third transistors across a source of direct current potential, a capacitor, means connecting said capacitor across said base and collector of said third transistor and across said source of direct current potential, and a gating circuit connected to said capacitor of said first switch means for turning on said first switch means at substantially the zero point in the current cycle of the current controlled by said first switch means.

Claim 15

The apparatus of claim 11 wherein said synchronization means comprises a delta connected resistive network connected between said first, second and third connecting means and said first and second switch control means.

Claim 16

The apparatus of claim 13 wherein said delta connected resistive network comprises a first resistor connected from said first switch control means to a junction between said second switch means and said second load terminal, a second resistor connected from said second switch control means to a junction between said first switch means and said first load terminal, a third resistor connected from a junction of said first resistor and said first switch control means to said third connecting means, and a fourth resistor connecting a junction of said second resistor and said second switch control means to said third connecting means.

Claim 17

The apparatus of claim 14 wherein said first switch control means comprises a first resistor connected between said fifth resistor and said first conductor, a first transistor having an emitter and a base connected across said fifth resistor and a collector, said emitter being connected to said first conductor, a second transistor having a base connected to said base of said first transistor, a collector and an emitter, a third transistor having a base connected to said first conductor, an emitter connected to the emitter of said second transistor and a collector connected to the collector of said first transistor, means connecting said collectors of said second and third transistors across a source of direct current potential, a capacitor, means connecting said capacitor across said base and collector of said third transistor and across said source of direct current potential, and a gating circuit connected to said capacitor and said first switch means for turning on said first switch means at substantially the zero point in the current cycle of the current controlled by said first switch means.

Claim 18

The apparatus of claim 14 wherein said first switch control means comprises a first switch control means resistor connected from said first connecting means to said first resistor, a first gating circuit connected to said first switch means and a first zero sensing circuit connected between said first switch control means resistor and said first gating circuit, and said second switch control means comprises a second switch control means resistor connected to said second resistor, a second gating circuit connected to said second switch means and a second zero sensing circuit connected between said second switch control means resistor and said second gating circuit.

Claim 19

The apparatus of claim 16 wherein said first zero sensing means comprises a first zero sensor for sensing the zero point in the current cycle of the current through said first switch control means resistor and a first time proportioning condition responsive means for insuring that the first switch means will not be turned on until both the zero point in the current cycle of the current in the first connecting means has been substantially attained and a time proportioning signal from said first time proportioning condition responsive means has been received and the second zero sensing means comprises a second zero sensor for sensing the zero point in the current cycle of the current through said second switch control means resistor and a second time proportioning condition responsive means for insuring that the second switch means will not be turned on until both of the zero point in the current cycle of the current in the second connecting means has been substantially attained and a time proportioning signal from said second time proportioning condition responsive means has been received.

Claim 20

The apparatus of claim 17 wherein said first and second switch means comprises respective first and second solid state switches having respective first and second gates connected to said respective first and second gating circuits.